Row driver circuit for a sensor including a shared row-reset bus and a charge pump boosting circuit

• US 6,937,278 B2
• Filed: 06/05/2001
• Issued: 08/30/2005
• Est. Priority Date: 04/02/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Huang, Steve, Van Blerkom, Daniel
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): WILSON, JACQUELINE B
• Application Number:
  US09/876,848
• Publication Number:
  US 20020140689A1
• Time in Patent Office: 1,547 Days
• Field of Search: 348/302, 348/304, 348/308, 348/312, 377/64, 377/75, 377/77, 377/79, 377/57, 377/60, 377/62, 257/215, 257/229, 257/231, 257/242, 257/252
• US Class Current: 348/304
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/51 Control of the gain
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62
• CPC Class Codes: H04N 3/1575 Picture signal readout register, e.g. shift registers, interline shift registers

Abstract

A row driver according to an embodiment drives a shared row-reset bus to one of a select voltage and a boosted voltage to select a row for readout and to reset the pixels in the row, respectively. The boosted voltage is higher than the select voltage. A row select circuit includes PMOS transistors through which a path may be opened between a supply line carrying the select voltage and the bus. A reset enable circuit includes PMOS transistors through which a path may be opened between a supply line carrying the boosted voltage and the bus. In order to prevent a parasitic diode leakage between the two supply lines during reset, the n-wells of the PMOS transistors in the row select circuit may be coupled to the supply line carrying the boost voltage.

Claims

1. A method comprising:

selecting a row from a plurality of rows in a pixel array;

opening a path between a first line having a first voltage and a bus through one or more row select transistors;

selecting the row for reset;

opening a path between a second line having a second voltage and the bus through one or more reset enable transistors, said second voltage being higher than said first voltage; and

providing the second voltage to the one or more row select transistors.

2. The method of claim 1, wherein the one or more row select transistors comprise PMOS transistors, each including an n-well.

3. The method of claim 2, wherein said providing the second voltage to the one or more row select transistors comprises boosting the n-wells of the PMOS transistors to the second voltage.

4. The method of claim 1, wherein the second voltage comprises a boosted reset voltage.

5. A row driver comprising:

a bus;

a first line operative to carry a select voltage;

a second line operative to be driven to a boosted voltage, said boosted voltage being higher than the select voltage; and

a first circuit operative to couple the bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line,

wherein the boosted voltage comprises a reset enable signal.

8. The row driver of claim 5, wherein the select voltage comprises Vdd.

9. The row driver of claim 5, wherein the select voltage is about 3.3 volts and the boosted voltage is about 4.2 volts.

10. The row driver of claim 5, wherein the transistor comprises a PMOS transistor including a source connected to the first line and an n-well connected to the second line.

6. A row driver comprising:

a bus;

a first line operative to carry a select voltage;

a second line operative to be driven to a boosted voltage, said boosted voltage being higher than the select voltage;

a first circuit operative to couple the bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line; and

a second circuit operative to couple the bus to the second line in response to a row reset signal.

11. The row driver of claim 6, wherein the second circuit is coupled to a bus of another row driver.

12. The row driver of claim 11, wherein the second circuit is operative to couple to the second line to the bus in response to a select signal on the bus of said another row driver.

13. The row driver of claim 6, wherein the second circuit comprises a plurality of PMOS transistors, each PMOS transistor including a source and an n-well coupled to the second line.

7. A row driver comprising:

a bus;

a first line operative to carry a select voltage;

a second line operative to be driven to a boosted voltage, said boosted voltage being higher than the select voltage; and

a first circuit operative to couple the bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line,

wherein the transistor is coupled to the second line such that there is no parasitic diode leakage between the first line and the second line through the transistor in response to the second line being driven to the boosted voltage.

14. A row driver comprising:

a bus;

a first line operative to carry a select voltage;

a second line operative to be driven to a boosted voltage, said boosted voltage being higher than the select voltage; and

a first circuit operative to couple the bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line,

wherein the bus comprises a shared row-reset bus.

15. A sensor comprising:

a pixel array including a plurality of pixels arranged in rows and columns

a plurality of buses, each bus coupled to pixels in one row of the pixel array;

a first line operative to carry a select voltage;

a second line operative to carry a row enable voltage;

a charge pump boost circuit operative to drive the second line to a boosted voltage, said boosted voltage being higher than the select voltage;

a plurality of row drivers, each row driver coupled to an associated one of the buses and including a first circuit operative to couple said bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line, wherein the bus comprises a shared row-reset bus.

19. The sensor of claim 15, wherein the select voltage comprises Vdd.

20. The sensor of claim 15, wherein the select voltage is about 3.3 volts and the boosted voltage is about 4.2 volts.

21. The sensor of claim 15, wherein the transistor comprises a PMOS transistor including a source connected to the first line and an n-well connected to the second line.

25. The sensor of claim 15, wherein each pixel comprises an active pixel sensor including a photoreceptor and an in-pixel follower transistor.

16. A sensor comprising:

a pixel array including a plurality of pixels arranged in rows and columns

a plurality of buses, each bus coupled to pixels in one row of the pixel array;

a first line operative to carry a select voltage;

a second line operative to carry a row enable voltage;

a charge pump boost circuit operative to drive the second line to a boosted voltage, said boosted voltage being higher than the select voltage;

a plurality of row drivers, each row driver coupled to an associated one of the buses and including a first circuit operative to couple said bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line; and

a second circuit operative to couple the bus to the second line in response to a row reset signal.

22. The sensor of claim 16, wherein the second circuit is coupled to a bus of another row driver.

23. The sensor of claim 22, wherein the second circuit is operative to couple to the second line to the bus in response to a select signal on the bus of said another row driver.

24. The sensor of claim 16, wherein the second circuit comprises a plurality of PMOS transistors, each PMOS transistor including a source and an n-well coupled to the second line.

17. A sensor comprising:

a pixel array including a plurality of pixels arranged in rows and columns

a plurality of buses, each bus coupled to pixels in one row of the pixel array;

a first line operative to carry a select voltage;

a second line operative to carry a row enable voltage;

a charge pump boost circuit operative to drive the second line to a boosted voltage, said boosted voltage being higher than the select voltage; and

a plurality of row drivers, each row driver coupled to an associated one of the buses and including a first circuit operative to couple said bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line,

wherein the transistor is coupled to the second line such that there is no parasitic diode leakage between the first line and the second line through the transistor in response to the second line being driven to the boosted voltage.

18. A sensor comprising:

a pixel array including a plurality of pixels arranged in rows and columns

a plurality of buses, each bus coupled to pixels in one row of the pixel array;

a first line operative to carry a select voltage;

a second line operative to carry a row enable voltage;

a charge pump boost circuit operative to drive the second line to a boosted voltage, said boosted voltage being higher than the select voltage; and

a plurality of row drivers, each row driver coupled to an associated one of the buses and including a first circuit operative to couple said bus to the first line in response to a row select signal, said first circuit including a transistor coupled to the second line.

wherein the boosted voltage comprises a reset enable signal.

26. A method of operating an image sensor comprising:

selecting a row from a plurality of rows in a pixel array;

connecting a first line having a first voltage to a bus through one or more row select transistors;

selecting the row for reset;

connecting a second line having a second voltage to the bus through one or more reset enable transistors, said second voltage being higher than said first voltage; and

providing the second voltage to the one or more row select transistors.