High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown

CAFC
  • US 6,940,751 B2
  • Filed: 01/26/2004
  • Issued: 09/06/2005
  • Est. Priority Date: 04/26/2002
  • Status: Active Grant
First Claim
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1. A programmable memory cell useful in a memory array having column bitlines and row wordlines, the memory cell comprising:

  • a transistor having a gate, a gate dielectric between the gate and over a substrate, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate; and

    wherein the second doped semiconductor region of the transistor is connected to one of said row wordlines, and wherein said gate dielectric is formed such that the gate dielectric is more susceptible to breakdown near the first doped semiconductor region than said second doped semiconductor region.

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