High-performance, superscalar-based computer system with out-of-order instruction execution

• US 6,941,447 B2
• Filed: 11/05/2003
• Issued: 09/06/2005
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Wang, Sze-Shun, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki, Nguyen, Le-Trong
• Primary Examiner(s): PAN, DANIEL H
• Application Number:
  US10/700,520
• Publication Number:
  US 20040093482A1
• Time in Patent Office: 671 Days
• Field of Search: 712/23, 712/41, 712/215, 712/219, 712/218, 712/213, 712/245, 712/206, 711/138, 711/123, 711/125, 710/305, 710/316
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A computer system, comprising:

a memory;

a superscalar microprocessor for processing instructions; and

a bus coupled between the memory and the microprocessor;

wherein the microprocessor includes;

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;

an instruction buffer coupled to receive and buffer fetched instructions from the instruction fetch unit;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;

a resource identifying circuit configured to concurrently identify execution resources for more than one of a plurality of buffered instructions, the identified execution resources for each of the buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction, thereby making a plurality of instructions concurrently available for execution;

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of a plurality of available instructions to the functional units for execution, based on availability of the execution resources identified by the resource identifying circuit and without regard to the sequential program order;

a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file; and

bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via an alternate data path that bypasses the register file, wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file.

2. The system of claim 1, wherein:

the plurality of functional units includes an integer functional unit and a floating-point functional unit; and

the bypass control logic is further configured such that an integer result from the integer functional unit is distributed to the floating-point functional unit via the alternate data path.

3. The system of claim 1, wherein:

the plurality of functional units includes an integer functional unit and a floating-point functional unit; and

the bypass control logic is further configured such that a floating-point result from the floating-point functional unit is distributed to the integer functional unit via the alternate data path.

4. The system of claim 1, wherein the microprocessor further includes:

operand data routing paths coupled between the register file and the functional units and configured to concurrently transfer operand data to more than one of the functional units.

5. The system of claim 4, wherein the operand data routing paths transfer operand data directly from the register file to the functional units.

6. The system of claim 1, further comprising retirement control logic coupled to the register file and configured to concurrently retire a plurality of instructions according to the sequential program order.

7. The system of claim 6, wherein the register file includes:

a temporary buffer having a first plurality of entries; and

a retired register array having a second plurality of entries;

and wherein the retirement control logic is further configured such that when an instruction is retired, corresponding result data is transferred from the temporary buffer to the retired register array.

8. The system of claim 1, wherein the resource identifying circuit is further configured to concurrently identify execution resources for a first one and a second one of the plurality of buffered instructions, wherein the second one of the instructions has a data dependency on the first one of the instructions.

9. A superscalar microprocessor for processing instructions, the microprocessor comprising:

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;

an instruction buffer coupled to receive and buffer fetched instructions from the instruction fetch unit;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;

a resource identifying circuit, disposed at a stage subsequent to said instruction buffer, configured to concurrently identify execution resources for a plurality of buffered instructions, thereby making a plurality of instructions concurrently available for issue, wherein the identified execution resources for each of the available instructions include a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction; and

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and without regard to the sequential program order.

10. The microprocessor of claim 9, wherein:

the plurality of functional units includes an integer functional unit and a floating-point functional unit.

11. The microprocessor of claim 9, further comprising:

operand data routing paths coupled between the register file and the functional units and configured to concurrently transfer operand data to more than one of the functional units.

12. The microprocessor of claim 9, further comprising:

retirement control logic coupled to the register file and configured to retire a plurality of instructions according to the sequential program order.

13. The microprocessor of claim 12 wherein the register file includes:

a temporary buffer having a first plurality of entries; and

a retired register array having a second plurality of entries;

wherein the retirement control logic is further configured such that when an instruction is retired, corresponding result data is transferred from the temporary buffer to the retired register array.

14. A method for processing instructions in a superscalar microprocessor, the method comprising:

fetching instructions from an instruction store according to a sequential program order;

buffering a plurality of fetched instructions in an instruction buffer;

concurrently identifying execution resources, by a resource identifying circuit disposed at a stage subsequent to said instruction buffer, for more than one of a plurality of buffered instructions, the identified execution resources for each of the more than one of the plurality of buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction;

concurrently making available for execution a plurality of instructions for which execution resources are identified;

concurrently issuing more than one of the plurality of available instructions for execution by a plurality of functional units, based on availability of the identified execution resources for each available instruction and without regard to the sequential program order;

executing the issued instructions in the plurality of functional units, thereby generating result data; and

transferring the result data from the functional units to a register file, the register file including a plurality of entries, wherein each of the plurality of entries is accessible by reference to a respective location in the register file.

15. The method of claim 14, wherein:

the plurality of functional units includes an integer functional unit and a floating point functional unit.

16. The method of claim 14, further comprising:

concurrently transferring operand data from the register file to more than one of the functional units via a plurality of operand data routing paths.

17. The method of claim 14, further comprising retiring instructions according to the sequential program order.

18. The method of claim 17 wherein the register file includes:

a temporary buffer having a first plurality of entries; and

a retired register array having a second plurality of entries;

wherein the retiring an instruction includes transferring corresponding result data from the temporary buffer to the retired register array.

19. A computer system, comprising:

a memory;

a superscalar microprocessor for processing instructions; and

a bus coupled between the memory and the microprocessor;

wherein the microprocessor includes;

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;

an instruction buffer coupled to receive fetched instructions from the instruction fetch unit and configured to buffer a plurality of fetched instructions;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;

a resource identifying circuit, disposed at a stage subsequent to said instruction buffer, configured to concurrently identify execution resources for a plurality of buffered instructions, the identified execution resources for each of the buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction, thereby making a plurality of instructions concurrently available for execution; and

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the execution resources identified by the resource identifying circuit and without regard to the sequential program order.

20. The computer system of claim 19, wherein:

the plurality of functional units includes an integer functional unit and a floating-point functional unit.

21. The computer system of claim 19, further comprising:

operand data routing paths coupled between the register file and the functional units and configured to concurrently transfer operand data to more than one of the functional units.

22. The computer system of claim 19, further comprising retirement control logic coupled to the register file and configured to retire a plurality of instructions according to the sequential program order.

23. The computer system of claim 22 wherein the register file includes:

a temporary buffer having a first plurality of entries; and

a retired register array having a second plurality of entries;

wherein the retirement control logic is further configured such that when an instruction is retired, corresponding result data is transferred from the temporary buffer to the retired register array.