Synchronizing clocks across a communication link

  • US 6,944,188 B2
  • Filed: 02/21/2001
  • Issued: 09/13/2005
  • Est. Priority Date: 02/21/2001
  • Status: Expired due to Fees
First Claim
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1. An apparatus for synchronizing a slave clock at a receiving end of a communication link to a master clock at a transmitting end of the communication link, comprising:

  • master apparatus at the first end of the communication link including storage configured to retain a known data pattern, a sequencer configured to dispose the known data pattern as part of data for transmission to the receiving end of the communication link, a timer including a counter configured to produce an output based on counting a known number of master clock cycles as an interval between transmissions of the known data pattern, a transmitter configured to transmit, responsive to the timer counter output, a synchronization signal reflecting the known data pattern from the sequencer at intervals indicated by the timer; and

    slave apparatus at the receiving end of the communication link including a receiver configured to receive the transmitted synchronization signal, storage configured to retain a data pattern comparable to the received synchronization signal, a controllable slave clock oscillator having a variable slave clock rate, correlator apparatus configured to identify a synchronization time at which the received synchronization signal arrives in terms defined with respect to periods of a sample clock having a rate which is n times the slave clock rate, the correlator apparatus including a correlation digital signal generator configured to generate digital correlation signal samples at the sample clock rate, a digital correlation sample local maximum indicating the sample closest to when the synchronization signal and the stored comparable data pattern match, a correlation peak interpolator of the digital correlation signal, the correlation peak interpolator output indicating the synchronization time to an interpolator resolution less then 1/n of a slave clock period, a slave clock expected time generator configured to indicate an expected time when the synchronization signal will be received if the slave clock is synchronized to the master dock, a slave clock error generator configured to generate a slave clock error signal based on a difference between the expected time for the synchronization signal and the received synchronization signal time indicated by the correlator apparatus, and an error filter configured to output a filtered slave clock error to the slave clock controllable oscillator to adjust the slave clock rate.

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