Configurable pipe delay with window overlap for DDR receive data
DCFirst Claim
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1. A system in a computing device for maximizing set up time and hold time for data reads from a double-data-rate (DDR) memory device, the system comprising:
- a strobe timing adjustment circuit, the strobe timing adjustment circuit having at least one programmable delay unit, the at least one programmable delay unit being controlled by software; and
a single-datum-to-double-data converting circuit, wherein timing of data from the converting circuit is controlled through an add-half cycle control, the add-half cycle control being activated through software;
wherein the strobe timing adjustment circuit adjusts timing of a strobe from the DDR memory device through the at least one programmable delay unit, and an adjusted strobe from the strobe timing adjustment circuit is used to latch data from the DDR memory device into said converting circuit.
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Abstract
A system for maximizing set up and hold times for data reads from a DDR memory device. The system adjusts timing of a strobe from a DDR memory device and converts data from the DDR memory device into a single-data-rate data. The timing adjustment is preferably controlled through software, and the system selectively determines if an extra half cycle should be added to the data path to optimize data reads.
40 Citations
16 Claims
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1. A system in a computing device for maximizing set up time and hold time for data reads from a double-data-rate (DDR) memory device, the system comprising:
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a strobe timing adjustment circuit, the strobe timing adjustment circuit having at least one programmable delay unit, the at least one programmable delay unit being controlled by software; and a single-datum-to-double-data converting circuit, wherein timing of data from the converting circuit is controlled through an add-half cycle control, the add-half cycle control being activated through software; wherein the strobe timing adjustment circuit adjusts timing of a strobe from the DDR memory device through the at least one programmable delay unit, and an adjusted strobe from the strobe timing adjustment circuit is used to latch data from the DDR memory device into said converting circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for maximizing set up time and hold time for data reads from a double-data-rate (DDR) memory device in a computing system, the method comprising the steps of:
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generating a first strobe for rising edge latches and a second strobe for falling edge latches from a single strobe, wherein timing for the first strobe and the second strobe can be adjusted; converting a single datum from the DDR memory device into a doublewide data, wherein the doublewide data are latched with the first strobe and the second strobe; and latching the doublewide data into a second pipe stage latch with 2X clock. - View Dependent Claims (11, 12, 13, 14)
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15. A system in a computing device for maximizing set up time and hold time for data reads from a double-data-rate (DDR) memory device, the system comprising:
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strobe signal means for generating a first strobe and a second strobe from a single strobe; timing means for adjusting timing of the first strobe and the second strobe; conversion means for converting a single datum received from a DDR memory device into a doublewide data, wherein the doublewide data are latched with the second strobe; and delay means for adding a half-cycle delay to the doublewide data. - View Dependent Claims (16)
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Specification