Configurable pipe delay with window overlap for DDR receive data

  • US 6,950,350 B1
  • Filed: 04/04/2002
  • Issued: 09/27/2005
  • Est. Priority Date: 01/08/2002
  • Status: Active Grant
First Claim
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1. A system in a computing device for maximizing set up time and hold time for data reads from a double-data-rate (DDR) memory device, the system comprising:

  • a strobe timing adjustment circuit, the strobe timing adjustment circuit having at least one programmable delay unit, the at least one programmable delay unit being controlled by software; and

    a single-datum-to-double-data converting circuit, wherein timing of data from the converting circuit is controlled through an add-half cycle control, the add-half cycle control being activated through software;

    wherein the strobe timing adjustment circuit adjusts timing of a strobe from the DDR memory device through the at least one programmable delay unit, and an adjusted strobe from the strobe timing adjustment circuit is used to latch data from the DDR memory device into said converting circuit.

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