CMOS inspection apparatus

• US 6,958,768 B1
• Filed: 10/20/2000
• Issued: 10/25/2005
• Est. Priority Date: 10/20/2000
• Status: Expired due to Term

• Current Assignee: ASTI Holdings Limited
• Original Assignee: ASTI Holdings Limited
• Inventors: Rao, Sreenivas, Jusoh, Noor Ashedah Binti
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Henn, Timothy J.
• Application Number:
  US09/693,323
• Time in Patent Office: 1,831 Days
• Field of Search: 348/241, 348/294, 348/296, 348/308, 348/86, 348/92, 348/93
• US Class Current: 348/86
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A system for inspecting components is provided. The system includes a CMOS imaging system generating image data, such as pixel data from a pixel array. An image analysis system is connected to the CMOS imaging system, the image analysis system receiving the image data and generating image analysis data. The CMOS imaging system generates the image data at a rate that allows the CMOS imaging device to be used for inspecting components.

Claims

1. A system for inspecting components comprising:

a CMOS imaging system generating image data;

an image analysis system coupled to the CMOS imaging device, the image analysis system receiving the image data and generating image analysis data;

a processor coupled to the image analysis system, the processor operating one or more additional software systems used for image data analysis, wherein the processor, the image analysis system, and the CMOS imaging system are an embedded imaging system; and

wherein the CMOS imaging system generates the image data at a rate that allows the CMOS imaging device to be used for inspecting components in response to line shift control data received from the image analysis system.

2. The system of claim 1 wherein the CMOS imaging system further comprises a CMOS active pixel sensor.

3. The system of claim 2 wherein the CMOS active pixel sensor is a Photobit model PB 1024 CMOS active pixel sensor.

4. The system of claim 1 wherein the CMOS imaging system further comprises an image analysis controller receiving pixel data from a sensor and generating the image data from the pixel data.

5. The system of claim 1 wherein the CMOS imaging sensor generates lines of image data at a speed greater than one line every 15.6 microseconds.

6. The system of claim 1 wherein the CMOS imaging sensor generates frames of image data at a rate greater than one frame every 30 milliseconds.

7. The system of claim 1 wherein the CMOS imaging sensor further comprises a pixel shift system that enables a readout sequence to start at a pixel series position that reduces noise and improves signal quality.

8. The system of claim 7 wherein the pixel shift system enables the readout sequence to start at a fifth pixel series position.

9. A method for generating image data of a component for use in inspecting the component comprising:

generating pixel data using a CMOS imaging system;

transferring the pixel data as a plurality of pixel lines, further comprising

generating a reset command;

initiating a pixel line at the next clock cycle after the reset command;

waiting a predetermined number of clock cycles to generate a next pixel line; and

wherein the predetermined number of clock cycles is less than 208 clock cycles;

assembling the pixel lines into a frame; and

wherein the frame is assembled in less than 30 milliseconds.

10. The method of claim 9 wherein generating pixel data using a CMOS imaging system further comprises generating pixel data using a CMOS active pixel sensor.

11. The method of claim 9 wherein generating pixel data using a CMOS imaging system further comprises generating pixel data using a Photobit model PB 1024 CMOS active pixel sensor.

12. The method of claim 9 wherein transferring the pixel data as the plurality of pixel lines further comprises initiating a read sequence for each of the pixel lines at a predetermined pixel series position.

13. The method of claim 9 wherein transferring the pixel data as the plurality of pixel lines further comprises initiating a read sequence for each of the pixel lines at a fourth pixel series position.

14. The method of claim 9 wherein assembling the pixel lines into the frame further comprises reading a first frame following the generation of a reset command.

15. The method of claim 9 wherein the frame is assembled in 13.5 milliseconds.