Self-aligned body tie for a partially depleted SOI device structure

• US 6,960,810 B2
• Filed: 05/30/2002
• Issued: 11/01/2005
• Est. Priority Date: 05/30/2002
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Fechner, Paul
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MALDONADO, JULIO J
• Application Number:
  US10/158,603
• Publication Number:
  US 20030222313A1
• Time in Patent Office: 1,251 Days
• Field of Search: 257/200, 257/347, 257/351, 257/510, 257/288, 257/324, 257/325, 257/296, 257/350, 257/368, 257/392, 257/393, 257/348, 257/349, 257/352, 257/353, 257/354, 257/524, 257/E27.112, 257/E21.545, 438/162, 438/163, 438/151, 438/459
• US Class Current: 257/351
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.

Claims

1. A self-aligned body tie for a partially depleted silicon-on-insulator device structure, comprising in combination:

an active region on a silicon-on-insulator substrate;

an N-channel device and a P-channel device formed on the active region;

a first body tie providing a conduction path from a p-well region of the N-channel device to a P+ body contact; and

a second body tie providing a conduction path from an n-well region of the P-channel device to an N+ body contact.

2. The structure of claim 1, wherein a gate is located substantially above the p-well region of the N-channel device and substantially above the n-well region of the P-channel device.

3. The structure of claim 2, wherein the gate extends onto a surrounding field oxide layer to provide interconnection between transistors and contacts.

4. The structure of claim 1, wherein the N-channel device includes an N+ drain, an N+ source, and a gate.

5. The structure of claim 1, wherein the P-channel device includes a P+ drain, the P+ source, and a gate.

6. The device of claim 1, wherein gate spacers are located substantially adjacent to both sides of the p-well region and the n-well region.

7. The structure of claim 6, wherein an N+ drain and the N+ source are located substantially adjacent to the gate spacers on opposite sides of the p-well region.

8. The structure of claim 6, wherein a P+ drain and the P+ source are located substantially adjacent to the gate spacers on opposite sides of the n-well region.

9. The structure of claim 1, wherein the P+ body contact is located substantially adjacent to the N+ source.

10. The structure of claim 1, wherein the N+ body contact is located substantially adjacent to the P+ source.

11. The structure of claim 1, wherein body tie spacers are located substantially adjacent to the P+ body contact and the N+ body contact.

12. The structure of claim 1, wherein the first body tie and the second body tie are located substantially between sidewalls and gate spacers.

13. A self-aligned body tie for a partially depleted silicon-on-insulator device structure, comprising in combination:

an active region on a silicon-on-insulator substrate;

an N-channel device and a P-channel device formed on the active region, wherein the N-channel device includes an N+ drain, an N+ source, and a gate, wherein the P-channel device includes a P+ drain, a P+ source, and the gate, and wherein the gate extends onto a surrounding field oxide layer to provide interconnection between transistors and contacts;

a first body tie providing a conduction path from a p-well region of the N-channel device to a P+ body contact, wherein the P+ body contact is located substantially adjacent to the N+ source, and wherein the first body tie and the N+ source directly contact a buried oxide layer in the active region;

a second body tie providing a conduction path from an n-well region of a P-channel device to an N+ body contact, wherein the N+ body contact is located substantially adjacent to the P+ source, and wherein the second body tie and the P+ source directly contact the buried oxide layer in the active region; and

wherein gate spacers are located substantially adjacent to both sides of the p-well region and the n-well region, wherein the N+ drain and the N+ source are located substantially adjacent to the gate spacers on opposite sides of the p-well region, wherein the P+ drain and the P+ source are located substantially adjacent to the gate spacers on opposite sides of the n-well region,

wherein body tie spacers are located substantially adjacent to the P+ body contact and the N+ body contact, and wherein the first body tie and the second body tie are located substantially between sidewalls and gate spacers.