Subsampling communication receiver architecture with relaxed IFA readout timing

• US 6,963,732 B2
• Filed: 04/25/2002
• Issued: 11/08/2005
• Est. Priority Date: 04/25/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Muhammad, Khurram, Leipold, Dirk
• Primary Examiner(s): Trinh, Sonny
• Assistant Examiner(s): Bhattacharya, Sam
• Application Number:
  US10/132,436
• Publication Number:
  US 20020177422A1
• Time in Patent Office: 1,293 Days
• Field of Search: 455/112, 455/118, 455/131, 455/137, 455/257, 455/190.1, 455/313, 455/314, 455/316, 455/323, 327/113, 375/350, 375/296
• US Class Current: 455/131
• CPC Class Codes: H03H 15/00 Transversal filters electromechanical filters H03H9/46, H03H9/70
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04L 27/24 Half-wave signalling systems

Abstract

A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform. The second waveform is driven by an amplifier stage (25), and the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.

Claims

1. An apparatus for downconverting a first periodic voltage waveform into a second periodic voltage waveform, comprising:

an input for receiving the first voltage waveform;

a sampler coupled to said input for obtaining from the first voltage waveform a plurality of temporally distinct samples respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform; and

a combiner coupled to said sampler for combining the samples to produce the second voltage waveform, including a drive amplifier for driving the second voltage waveform, and a switching apparatus connected between said sampler and said drive amplifier for connecting said sampler to said drive amplifier during temporally separated readout time intervals, said switching apparatus operable while said sampler is obtaining said samples for disconnecting said sampler from said drive amplifier to create between adjacent pairs of said readout time intervals respective idle time intervals that permit adjustment of said drive amplifier without losing information in the first voltage waveform.

2. The apparatus of claim 1, wherein said readout time intervals are equal in length to said idle time intervals.

3. The apparatus of claim 1, wherein said readout time intervals are longer than said idle time intervals.

4. The apparatus of claim 1, wherein said sampler includes a transconductance amplifier for transforming the first voltage waveform into a corresponding current waveform, and a plurality of capacitors coupled to said transconductance amplifier for integrating fractional-cycles of the current waveform.

5. The apparatus of claim 4, wherein said sampler is operable for integrating more than one of said fractional-cycles of the current waveform on a single one of said capacitors during at least one of said idle time intervals.

6. The apparatus of claim 4, wherein said switching apparatus is connected between said capacitors and said drive amplifier.

7. The apparatus of claim 6, wherein said switching apparatus includes a plurality of switches connected between said drive amplifier and respective ones of said capacitors.

8. The apparatus of claim 4, wherein said combiner is operable for dumping charge from at least one of said capacitors to said drive amplifier during each of said readout time intervals.

9. The apparatus of claim 8, wherein said combiner is operable for dumping charge from only one of said capacitors at a time to said drive amplifier during at least one of said readout time intervals.

10. The apparatus of claim 8, wherein said combiner is operable for dumping charge from more than one of said capacitors to said drive amplifier during at least one of said readout time intervals.

11. The apparatus of claim 10, wherein said combiner is operable for dumping said charge from said more than one of said capacitors simultaneously to said drive amplifier during said at least one readout time interval.

12. The apparatus of claim 10, wherein said combiner is operable for dumping charge from only one of said capacitors to said drive amplifier in at least one of said readout time intervals.

13. The apparatus of claim 1, wherein said switching apparatus includes a plurality of switches connected between said sampler and said drive amplifier.

14. The apparatus of claim 1, wherein said drive amplifier includes an input coupled to said sampler, an output for providing the second voltage waveform, and a capacitor coupled between said drive amplifier input and said drive amplifier output.

15. The apparatus of claim 1, wherein said drive amplifier includes a differential amplifier.

16. The apparatus of claim 1, wherein said combiner includes circuitry coupled to said drive amplifier for making an adjustment to said drive amplifier during said idle period.

17. The apparatus of claim 16, wherein said adjustment includes one of a reset and an offset correction.

18. The apparatus of claim 16, wherein said circuitry includes a switch coupled between an input and an output of said drive amplifier.

19. The apparatus of claim 1, wherein said readout time intervals are shorter than said idle time intervals.

26. The apparatus of claim 1, wherein said fractional cycles are one of half cycles and quarter cycles.

20. A communication receiving apparatus, comprising:

an input for receiving a communication signal formed as a first periodic voltage waveform;

a mixer coupled to said input for downconverting the first periodic voltage waveform into a second periodic voltage waveform, including a sampler coupled to said input for obtaining from the first voltage waveform a plurality of temporally distinct samples respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform, and a combiner coupled to said sampler for combining the samples to produce the second voltage waveform;

said combiner including a drive amplifier for driving the second voltage waveform, and a switching apparatus connected between said sampler and said drive amplifier for connecting said sampler to said drive amplifier during temporally separated readout time intervals, said switching apparatus operable while said sampler is obtaining said samples for disconnecting said sampler from said drive amplifier to create between adjacent pairs of said readout time intervals respective idle time intervals that permit adjustment of said drive amplifier without losing information in the first voltage waveform; and

a signal processing portion coupled to said drive amplifier for receiving and processing the second voltage waveform.

21. The apparatus of claim 20, wherein said communication signal is an RF communication signal.

22. The apparatus of claim 20, wherein said combiner includes circuitry coupled to said drive amplifier for making an adjustment to said drive amplifier during said idle period.

23. The apparatus of claim 22, wherein said circuitry includes a switch coupled between an input and an output of said drive amplifier.

24. The apparatus of claim 20, wherein said signal processing portion includes an analog signal processing portion, a baseband digital processing portion and an A/D converter coupled therebetween.

25. The apparatus of claim 20, wherein said fractional cycles are one of half cycles and quarter cycles.