Programmable logic device having heterogeneous programmable logic blocks
First Claim
Patent Images
1. A programmable logic device comprising:
- programmable interconnect circuitry;
programmable input-output circuitry coupled to the programmable interconnect circuitry; and
an array of programmable logic blocks, each logic block including a plurality of programmable logic elements coupled to the interconnect circuitry, wherein each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions, wherein the set of supplemental functions includes a distributed memory function, and selected bits of a distributed memory are stored in a programmable logic element.
1 Assignment
0 Petitions
Accused Products
Abstract
A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.
13 Citations
24 Claims
-
1. A programmable logic device comprising:
-
programmable interconnect circuitry; programmable input-output circuitry coupled to the programmable interconnect circuitry; and an array of programmable logic blocks, each logic block including a plurality of programmable logic elements coupled to the interconnect circuitry, wherein each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions, wherein the set of supplemental functions includes a distributed memory function, and selected bits of a distributed memory are stored in a programmable logic element. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A programmable logic device comprising:
-
programmable interconnect circuitry; programmable input-output circuitry coupled to the programmable interconnect circuitry; and an array of programmable logic blocks, each logic block including a plurality of programmable logic elements coupled to the interconnect circuitry, wherein at least one of the programmable logic elements in a logic block is programmable to implement a first set of functions, and at least one other of the programmable logic elements in the logic block is programmable to implement a second set of functions that is a proper subset of the first set of functions, wherein a function in the first set and not in the second set is a distributed memory function, wherein selected bits of a distributed memory are stored in a programmable logic element. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. A programmable logic block arrangement, comprising:
-
a switch circuit; a plurality of programmable logic elements coupled to the switch circuit, wherein each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions, wherein the set of supplemental functions includes a distributed memory function, and selected bits of a distributed memory are stored in a programmable logic element. - View Dependent Claims (14, 15, 16, 17, 18)
-
-
19. A programmable logic block arrangement, comprising:
-
a switch circuit; a first set of programmable logic elements coupled to the switch circuit, wherein the programmable logic elements of the first set implement a first set of functions; a second set of programmable logic elements coupled to the switch circuit, wherein the programmable logic elements of the second set implement a second set of functions that is a proper subset of the first set of functions, wherein a function in the first set and not in the second set is a distributed memory function, wherein selected bits of a distributed memory are stored in a programmable logic element. - View Dependent Claims (20, 21, 22, 23, 24)
-
Specification