Methods and apparatus for low power delay control

• US 6,971,036 B2
• Filed: 04/19/2002
• Issued: 11/29/2005
• Est. Priority Date: 04/19/2001
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: OnWafer Technologies, Inc. (KLA Corporation)
• Inventors: Freed, Mason L.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Bae, Ji H.
• Application Number:
  US10/126,455
• Publication Number:
  US 20020172097A1
• Time in Patent Office: 1,320 Days
• Field of Search: 710/262, 713/300, 713/323, 713/324, 713/320, 713/400, 713/322, 713/601, 370/503, 340/825.71, 725/150, 455/574
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A method of producing a time delay is provided. The method is performed with an information processor having a first timer and a second timer. The information processor is capable of maintaining a sleep mode. The method involves using the second timer to measure the timeout for the first timer. The method also includes repetitively causing the information processor to enter the sleep mode so as to be awakened by the first timer reaching timeout to substantially produce a time delay while the second timer is disabled.

Claims

1. A method of producing a time delay, the method performed with an information processor having a first timer and a second timer the information processor being capable of maintaining a sleep mode, the method comprising the steps of:

a) arranging the information processor so as to terminate the sleep mode when the first timer reaches timeout;

b) using the second timer to measure the timeout for the first timer;

c) disabling the second timer; and

d) repetitively causing the information processor to enter the sleep mode and causing the information processor to be awakened by the first timer reaching timeout so as to substantially produce the time delay.

2. The method of claim 1 wherein the information processor comprises a microprocessor.

3. The method of claim 1 wherein step d includes a number of repetitions equal to the nearest integer value of the time delay divided by the timeout for the first timer.

4. The method of claim 1 wherein the information processor comprises a microprocessor and step b comprises running the second timer while the microprocessor is in the sleep mode and running the first timer until the first timer reaches timeout.

5. The method of claim 1 wherein step b comprises running the second timer while running the first timer until the first timer reaches timeout.

6. The method of claim 4 wherein step d includes a number of repetitions equal to one subtracted from the nearest integer value of the time delay divided by the timeout for the first timer.

7. The method of claim 5 wherein step d includes a number of repetitions equal to one subtracted from the nearest integer value of the time delay divided by the timeout for the first timer.

8. The method of claim 1 wherein step b comprises setting the second timer to 0 at the beginning of calibrating the first timer.

9. The method of claim 1 wherein step b comprises disabling at least one possible interrupt source.

10. An apparatus for producing a time delay comprising an information processor having a first timer and a second timer, the information processor being capable of producing a sleep mode, the first timer having an upper time limit, the information processor being configured so as to awaken from the sleep mode in response to the first timer reaching the upper time limit, the information processor being capable of using the second timer to measure the upper time limit for the first timer, the information processor being capable of entering the sleep mode and running the first timer so as to cause the information processor to awaken from the sleep mode, the information processor being capable of entering the sleep mode and being awakened for a number of repetitions so as to produce the time delay.

11. The apparatus to claim 10 wherein the number of repetitions is an integer value of the time delay divided by the upper time limit.

12. The apparatus of claim 10 wherein the first timer requires less power for operation than the second timer.

13. The apparatus of claim 10 wherein the first timer has lower accuracy than the second timer.

14. The apparatus to claim 10 wherein the information processor comprises a microprocessor.

15. The apparatus to claim 10 wherein the information processor comprises at least one of a microprocessor, a computer, and a central processing unit.

16. The apparatus of claim 10 wherein the first timer comprises a watchdog timer.

17. The apparatus of claim 10 wherein the second timer comprises a high accuracy clock.

18. The apparatus of claim 10 further comprising a substantially fixed power supply.

19. An apparatus for producing a time delay with low-power consumption, the apparatus comprising a microprocessor having a watchdog timer and a high accuracy clock, the microprocessor being capable of producing a sleep mode, the watchdog timer having an upper time limit, the microprocessor being configured so as to awaken from the sleep mode in response to the watchdog timer reaching the upper time limit, the microprocessor being capable of using the high accuracy clock to measure the upper time limit for the watchdog timer, the microprocessor being capable of entering the sleep mode and running the watchdog timer so as to cause the microprocessor to awaken from the sleep mode, the microprocessor being capable of entering the sleep mode and being awakened for a number of repetitions so as to produce the time delay with the high accuracy clock disabled, wherein the watchdog timer requires less power than is required by the high accuracy clock, and wherein the high accuracy clock is more accurate for measuring time than is the watchdog timer.

20. The apparatus of claim 19 further comprising a battery connected so as to provide power to the watchdog timer and the high accuracy clock.