Semiconductor device and method of manufacturing the same

• US 6,974,996 B2
• Filed: 12/04/2003
• Issued: 12/13/2005
• Est. Priority Date: 01/23/2003
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Okabe, Yoshifumi, Aoki, Takaaki, Shiga, Tomofusa
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/726,590
• Publication Number:
  US 20040145012A1
• Time in Patent Office: 740 Days
• Field of Search: 357/23.6, 257/304, 257/382, 257/900, 257/E21.166, 257/E21.651, 257/E27.092, 365/149, 437/47, 438/243
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.

Claims

1. A vertical MOS device having a trench gate structure, the semiconductor device comprising:

a semiconductor body having a trench, the trench having an inlet, a sidewall and a bottom;

a gate insulation film disposed to cover the sidewall and the bottom of the trench, the gate insulation film comprising a laminate structure of a first silicon oxide film, silicon nitride film and a second silicon oxide film successively laminated in this order from a trench side; and

a gate electrode of a polycrystalline silicon which is doped with boron, the gate electrode filling the trench with the gate insulation film interposed, wherein;

the semiconductor body has a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type vertically aligned along the trench, and thereby a vertical MOS structure is formed by the gate electrode in the trench, the gate insulation film on the sidewall of the trench, and the first through third region;

the laminate structure of the gate insulation film is disposed to cover at least the second region in the trench;

the silicon nitride film in the laminate structure has a film thickness and film quality sufficient for suppressing boron from passing through the silicon nitride film; and

the first silicon oxide film at the trench side in the laminate structure has a film thickness that is greater than a film thickness of the second silicon oxide film at the gate electrode side.

2. The vertical MOS device according to claim 1, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the vertical MOS structure is a P channel type MOSFET.

3. The vertical MOS device according to claim 1, wherein the silicon nitride film in the laminate structure has a film thickness of 10–

30 nm.

4. The vertical MOS device according to claim 1, wherein the first silicon oxide film in the laminate structure has a film thickness of approximately 100 nm.

5. The vertical MOS device according to claim 1, wherein the film thickness of the first silicon oxide film in the laminate structure is controlled to satisfy a withstand voltage required for the laminate structure per se.

6. The vertical MOS device according to claim 1, wherein the silicon nitride film is a deposited film.

7. The vertical MOS device according to claim 1, wherein the laminate structure of the gate insulation film is locally located on the sidewall of the trench, and the gate insulation film comprises a first thick silicon oxide film disposed on the bottom of the trench, the first thick silicon oxide film having a film thickness greater than a film thickness of the laminate structure and covering a corner of the bottom of the trench.

8. The vertical MOS device according to claim 1, wherein the laminate structure of the gate insulation film is locally located on the sidewall of the trench, and the gate insulation film comprises a second thick silicon oxide film disposed on the inlet of the trench, the second thick silicon oxide film having a film thickness greater than a film thickness of the laminate structure and covering an inlet corner of the trench.

9. The vertical MOS device according to claim 7, wherein the laminate structure of the gate insulation film is locally located on the sidewall of the trench, and on the inlet of the trench is disposed a second thick silicon oxide film as the gate insulation film, the second thick silicon oxide film having a film thickness greater than the film thickness of the laminate structure and covering an inlet corner of the trench.

10. A vertical MOS device having a trench gate structure, the semiconductor device comprising:

a semiconductor body having a trench, the trench having an inlet, a sidewall and a bottom;

a gate insulation film disposed to cover the sidewall and the bottom of the trench, the gate insulation film comprising a laminate structure of a first silicon oxide film, silicon nitride film of 10–

30 nm in thickness and a second silicon oxide film successively laminated in this order from a trench side; and

a gate electrode of a polycrystalline silicon which is doped with boron, the gate electrode filling the trench with the gate insulation film interposed, wherein;

the semiconductor body has a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type vertically aligned along the trench, thereby forming a vertical MOS structure by the gate electrode in the trench, the gate insulation film on the sidewall of the trench, and the first through third region;

the laminate structure of the gate insulation film is disposed to locally cover the sidewall of the trench;

the first silicon oxide film at the trench side in the laminate structure has a film thickness that is greater than a film thickness of the second silicon oxide film at the gate electrode side; and

the gate insulation film on the bottom of the trench is a first thick silicon oxide film which has a film thickness greater than a film thickness of the laminate structure, the first thick silicon oxide film covering a corner of the bottom of the trench.

11. The vertical MOS device according to claim 10, wherein the first silicon oxide film in the laminate structure has a film thickness of approximately 100 nm.

12. The vertical MOS device according to claim 10, wherein the inlet of the trench is covered with a second thick silicon oxide film which has a film thickness greater than the film thickness of the laminate structure and covers an inlet corner of the trench.