NAND flash memory with improved read and verification threshold uniformity

• US 6,975,542 B2
• Filed: 05/08/2003
• Issued: 12/13/2005
• Est. Priority Date: 05/08/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/431,862
• Publication Number:
  US 20040223371A1
• Time in Patent Office: 950 Days
• Field of Search: 365/185.22, 365/185.17, 365/185.24, 365/185.33, 365/185.2
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to the first accessed cell. The first word line signal voltage level is adjusted in response to the position of the first accessed cell in its series of cells.

Claims

1. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:

determining a position of a first accessed cell, of a plurality of cells in a series configuration, with reference to a ground potential in the flash memory device; and

adjusting a first word line signal voltage level, coupled to the first accessed cell, in response to the position of the first accessed cell.

2. The method of claim 1 and further including generating a second word line voltage to a second accessed cell such that the second word line voltage is greater than the first word line voltage when the second accessed cell'"'"'s position is further from the ground potential in the series configuration than the first accessed cell'"'"'s position.

3. The method of claim 1 and further including generating a second word line voltage to a second accessed cell such that the second word line voltage is less than the first word line voltage when the second accessed cell'"'"'s position is closer to the ground potential in the series configuration than the first accessed cell'"'"'s position.

4. The method of claim 1 wherein the flash memory device is comprised of a NAND architecture.

5. The method of claim 1 wherein determining the position of the first accessed cell comprises decoding an address input to the flash memory device.

6. The method of claim 1 wherein the series configuration of the plurality of cells is coupled to a bit line at one end of the series configuration and at the ground potential at the opposite end of the series configuration.

7. The method of claim 1 wherein adjusting the first word line voltage comprises:

decoding an input address to generate the first word line signal having a nominal voltage level; and

compensating the nominal voltage level in response to the position of the first accessed cell.

8. The method of claim 7 wherein compensating the nominal voltage level comprises coupling the first word line signal having the nominal voltage level to a resistor divider voltage generator circuit to compensate the nominal voltage level.

9. The method of claim 7 wherein compensating the nominal voltage level comprises coupling the first word line signal having the nominal voltage level to an analog to digital converter acting as a voltage generator circuit to compensate the nominal voltage level.

10. A method for increasing read and erase verification threshold uniformity in a NAND flash memory device, the method comprising:

determining a position of a first accessed cell, of a plurality of cells in a series configuration, with reference to a ground potential in the flash memory device;

generating a word line signal having a first voltage level in response to an address input; and

compensating the first voltage level in response to the position of the first accessed cell.

11. The method of claim 10 wherein compensating the first voltage level comprises increasing the first voltage level in response to the position of the first accessed cell being further from the ground potential.

12. The method of claim 10 wherein compensating the first voltage level comprises adjusting the first voltage level towards a nominal voltage level in response to the position of the first accessed cell being closer to the ground potential.

13. A flash memory device comprising:

a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;

a column decoder that generates the bit line;

a row decoder that generates a word line having a nominal voltage level; and

a voltage generator circuit, coupled between the row decoder and the memory array, that adjusts the nominal voltage level in response to the position of a first memory cell indicated by the word line.

14. The device of claim 13 wherein the device is a NAND flash memory device.

15. The device of claim 13 wherein the voltage generator circuit is a voltage divider network.

16. The device of claim 13 wherein the voltage generator circuit is an analog-to-digital converter that uses a plurality of word lines generated by the row decoder to adjust the nominal voltage level.

17. A NAND flash memory device comprising:

a memory array comprising a plurality of memory cells coupled together in a plurality of series configurations, one end of each series configuration coupled to a bit line of a plurality of bit lines and an opposite end of each series configuration coupled to a ground potential reference;

a column decoder coupled to the memory array that generates the plurality of bit lines;

a row decoder that generates a plurality of word lines each having a nominal voltage level, a first word line capable of accessing a first cell in a first series configuration; and

a voltage generator circuit, coupled between the row decoder and the memory array, that generates a predetermined voltage level on the first word line in response to a position of the first cell in the first series configuration.

18. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:

reading a first cell of a plurality of cells coupled together in a series configuration;

determining a position of the first cell with reference to a ground potential in the flash memory device; and

generating a reference current in response to the position.

19. The method of claim 18 wherein determining the position of the first accessed cell comprises decoding an input address.

20. The method of claim 18 and further including:

comparing a measured current from the first cell with the reference current; and

determining a value of the read first cell in response to the comparison.

21. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:

reading a first cell of a plurality of cells coupled together in a series configuration;

determining a position of the first cell with reference to a ground potential in the flash memory device; and

generating a reference voltage in response to the position.

22. The method of claim 21 and further including:

comparing a measured voltage from the first cell with the reference voltage; and

determining a value of the read first cell in response to the comparison.

23. A method for increasing read and erase verification threshold uniformity in a NAND flash memory device, the method comprising:

reading a first cell of a plurality of cells, coupled together in a series configuration, in response to an address;

decoding the address to determine a position of the first cell with reference to a ground potential in the flash memory device;

generating a reference current in response to the position; and

comparing the reference current to a measured current of the first cell.

24. A method for increasing read and erase verification threshold uniformity in a NAND flash memory device, the method comprising:

reading a first cell of a plurality of cells, coupled together in a series configuration, in response to an address;

decoding the address to determine a position of the first cell with reference to a ground potential in the flash memory device;

generating a reference voltage in response to the position; and

comparing the reference voltage to a measured voltage of the first cell.

25. A flash memory device comprising:

a memory array comprising a plurality of cells coupled together in a plurality of series configurations; and

a reference generator that generates a measurement reference for each of the plurality of cells based on their locations in each of the plurality of series configurations.

26. The device of claim 25 wherein the reference generator comprises a plurality of memory locations that store a table indicating a reference current for each of the plurality of cells.

27. The device of claim 25 wherein the reference generator comprises a reference generator circuit.