Trench MOSFET having low gate charge

• US 6,979,621 B2
• Filed: 01/05/2004
• Issued: 12/27/2005
• Est. Priority Date: 11/15/2001
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/751,687
• Publication Number:
  US 20040150038A1
• Time in Patent Office: 722 Days
• Field of Search: 438/270, 438/273, 438/279, 257/330, 257/333, 257/340, 257/341
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

Claims

1. A method of forming a trench MOSFET device comprising:

providing a silicon substrate of a first conductivity type;

depositing a silicon epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;

forming a body region of a second conductivity type within an upper portion of said epitaxial layer;

etching a trench extending into said epitaxial layer from an upper surface of said epitaxial layer, said trench extending through said body region and said trench having trench sidewalls and a trench bottom;

forming an oxide region lining said trench, said oxide region comprising a lower segment covering at least the trench bottom and upper segments covering at least upper regions of said trench saidwalls,

wherein said oxide region lining said trench is formed by a process comprising;

forming a thermal oxide layer within said trench;

providing a deposited oxide layer over said thermal oxide layer;

forming an etch resistant region in the trench bottom over said deposited oxide layer; and

etching said deposited oxide layer where not covered by said etch resistant region;

depositing a conductive region within said trench adjacent said oxide region; and

forming a source region of said first conductivity type within an upper portion of said body region and adjacent said trench,

wherein said lower segment of said oxide region is thicker than said upper segments of said oxide region such that shoulders are established in said oxide region adjacent said conductive region along said trench sidewalls.

2. The method of claim 1, wherein said etch resistant region is a photoresist region.

3. The method of claim 1, wherein said etch resistant region is a polysilicon region.

4. The method of claim 1, wherein a thermal oxidant step is carried out after said deposited oxide-etching step.