Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

• US 6,982,465 B2
• Filed: 12/06/2001
• Issued: 01/03/2006
• Est. Priority Date: 12/08/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ohta, Hiroyuki, Kumagai, Yukihiro, Ikeda, Shuji, Miura, Hideo, Takeda, Toshifumi, Ichinose, Katsuhiko, Ootsuka, Fumio, Onai, Takahiro
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US10/433,786
• Publication Number:
  US 20040075148A1
• Time in Patent Office: 1,489 Days
• Field of Search: 257/369, 257/382, 257/384, 257/412, 257/413
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.

In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Claims

1. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor both formed on a substrate,

wherein said transistors each comprise an insulated film wrapping a gate electrode and extending to a location adjacent to a source/drain area, and said insulated film is mainly composed of silicon nitride, and the thickness of said insulated film of said n-channel field effect transistor differs from the thickness of said insulated film of said p-channel field effect transistor.

2. The semiconductor device according to claim 1,

wherein said insulated film is mainly composed of silicon nitride, and the size of an area extending adjacent to a source/drain area of said insulated film is different between said insulated film of said n-channel field effect transistor and said insulated film of said p-channel field effect transistors.

3. The semiconductor device according to claim 1,

wherein said insulated film is each mainly composed of silicon nitride, and an etching rate for said insulated film of said n-channel field effect transistor is different from that for said insulated film of said p-channel field effect transistor.

4. The semiconductor device according to claim 1, characterized in that said insulated film is mainly composed of silicon nitride.

5. A semiconductor device comprising:

an n-channel field effect transistor; and

a p-channel field effect transistor both formed on a substrate,

wherein a gate electrode of said n-channel field effect transistor is formed to undergo higher compression film stress than that of said p-channel field effect transistor.

6. A semiconductor device comprising:

an n-channel field effect transistor; and

a p-channel field effect transistor both formed on a substrate,

wherein impurities contained in a gate electrode of said n-channel field effect transistor have a concentration gradient in a perpendicular direction in a main plane of said silicon substrate, and impurities contained in a gate electrode of said p-channel field effect transistor have no concentration gradient in said perpendicular direction in said main plane of said silicon substrate within measurement limits or have a smaller concentration gradient than those in said gate electrode of said n-channel field effect transistor.

7. A semiconductor device comprising:

an n-channel field effect transistor; and

a p-channel field effect transistor both formed on a substrate,

wherein said gate electrode of said n-channel field effect transistor has a smaller average crystal particle size than that of said p-channel field effect transistor.

8. A semiconductor device comprising:

an n-channel field effect transistor;

a p-channel field effect transistor; and

element separating means for electrically separating adjacent transistor elements from each other, said n- and p-channel field effect transistor and said element separating means all being formed on a substrate,

wherein the distance between a channel portion of said n-channel field effect transistor and said element separating means is larger than that between a channel portion of said p-channel field effect transistor and said element separating means.

9. A semiconductor device comprising:

an n-channel field effect transistor; and

a p-channel field effect transistor both formed on a substrate,

wherein a Raman shift in a Raman spectrum obtained when a channel portion of said n-channel field effect transistor is irradiated with laser beams is smaller than that obtained when a channel portion of said p-channel field effect transistor is irradiated with laser beams.

10. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor both formed on a substrate,

wherein said transistors each have a silicide area formed in a source or drain area, and said silicide area of said n-channel field effect transistor is thicker than that of said p-channel field effect transistor.

11. The semiconductor device according to claim 10,

wherein said suicide area is mainly composed of cobalt suicide (COSi₂), titanium suicide (TiSi2), or nickel silicide.

12. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor both formed on a substrate,

wherein if tensile stress acts on an insulated film wrapping a gate electrode of each of said transistors and extending to an area adjacent to a source/drain area, then in a potion of said insulated film which is adjacent to the longitudinal side of the gate electrode, the p-channel field effect transistor has a smaller Young'"'"'s modulus than the n-channel field effect transistor, and

if compression stress acts on said insulated film wrapping said gate electrode of each of said transistors and extending to said area adjacent to said source/drain area, then in a portion of said insulated film which is adjacent to the longitudinal side of the gate electrode, the p-channel field effect transistor has a larger Young'"'"'s modulus than the n-channel fiefd effect transistor.

13. The semiconductor device according to claim 12,

wherein a material of the insulated material located adjacent to the longitudinal side of the gate electrode and having a large Young'"'"'s modulus is mainly composed of silicon nitride, and a material of the insulated material located adjacent to the longitudinal side of the gate electrode and having a small Young'"'"'s modulus is mainly composed of silicon oxide.

14. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor both formed on a substrate,

wherein:

said n-channel field effect transistor includes a plurality of n-channel field effect transistors and said p-channel field effect transistor includes a plurality of p-channel field effect transistors,

an insulated film undergoing tensile stress is formed on said n-channel field effect transistors and said p-channel field effect transistors, and

a portion of said insulated film which is thinner than a portion of said insulated film which is formed on a first p-channel field effect transistor or a second p-channel field effect transistor adjacent to said first p-channel field effect transistor is formed between said first p-channel field effect transistor and said second p-channel field effect transistor, or said insulated film is not installed on said first p-channel field effect transistor or said second p-channel field effect transistor.

15. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor bath formed on a substrate,

wherein:

said n-channel field effect transistor includes a plurality of n-channel field effect transistors and said p-channel field effect transistor includes a plurality of p-channel field effect transistors,

an insulated film undergoing tensile stress is formed on said n-channel field effect transistors and said p-channel field effect transistors, and

a portion of said insulated film which is thinner than a portion of said insulated film which is formed in an area located between a first n-channel field effect transistor and a second n-channel field effect transistor is formed in an area located between a first p-channel field effect transistor and a second p-channel field effect transistor adjacent to said first p-channel field effect transistor, said first n-channel field effect transistor corresponding to said first p-channel field effect transistor, said second n-channel field effect transistor corresponding to said second p-channel field effect transistor, or said insulated film is not formed in said area located between said first p-channel field effect transistor and said second p-channel field effect transistor.

16. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor both formed on a substrate,

wherein:

said n-channel field effect transistor includes a plurality of n-channel field effect transistors and said p-channel field effect transistor includes a plurality of p-channel field effect transistors,

an insulated film undergoing compression stress is formed on said n-channel field effect transistors and said p-channel field effect transistors, and

a portion of said insulated film which is thinner than a portion of said insulated film which is formed in an area located between a first p-channel field effect transistor and a second p-channel field effect transistor adjacent to said first p-channel field effect transistor is formed in an area located between a first n-channel field effect transistor corresponding to said first p-channel field effect transistor and a second n-channel field effect transistor corresponding to said second p-channel field effect transistor, or said insulated film is not formed in said area located between said first n-channel field effect transistor and said second n-channel field effect transistor.