Embedding a JTAG host controller into an FPGA design

• US 6,983,441 B2
• Filed: 06/28/2002
• Issued: 01/03/2006
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Telogy Networks, Inc. (Texas Instruments, Inc.)
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wescott, Douglas Albert
• Primary Examiner(s): Garbowski, Leigh M.
• Application Number:
  US10/183,902
• Publication Number:
  US 20040001432A1
• Time in Patent Office: 1,285 Days
• Field of Search: 716/1, 716/4, 716/16, 716/17, 714/724, 714/725, 714/726, 714/727, 714/733, 326/16
• US Class Current: 716/117
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary scan of targeted hardware using JTAG commands and architecture is described. The FPGA-based JTAG host controller is bussed directly into the FPGA core, bypassing the board'"'"'s JTAG communication port.

Claims

1. A system for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising:

a processor that includes source code for a JTAG host controller;

an FPGA attached to a peripheral printed circuit board, the FPGA including;

a memory array that is programmed with the source code for the JTAG host controller, by the external processor;

a processor core; and

JTAG interface logic;

a serial connector that connects the processor to the FPGA; and

a hardware target that is JTAG-compliant and attached to the peripheral printed circuit board;

wherein the FPGA sends JTAG host controller signals through the JTAG interface logic to the hardware target.

2. The system of claim 1, wherein the memory array includes at least one of a random access memory, a read only memory, an erasable programmable read only memory, and a first-in first-out buffer.

3. The system of claim 1, wherein the FPGA is removable from the printed circuit board.

4. The system of claim 1, wherein the hardware target includes one of a digital signal processor, an application specific integrated circuit, and an integrated circuit.

5. The system of claim 1, wherein JTAG host controller signals are sent from the FPGA to the target hardware without use of a controller that is external to the peripheral printed circuit board.

6. The system of claim 1, wherein the serial connector comprises one of a Universal Serial Bus (USB) connector, a Firewall (1394) connector, and an Ethernet connector.

7. A method for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising:

programming the FPGA on a peripheral printed circuit board to include;

a memory array;

a processor core; and

JTAG interface logic;

loading the memory array of the FPGA with source code of a JTAG host controller from an external processor through a serial connector; and

communicating JTAG signals through the JTAG interface logic to the hardware target that is JTAG-compliant and is located on the peripheral printed circuit board.

8. The method of claim 7, wherein the memory array includes one of a random access memory, a read only memory, an erasable programmable read only memory, and a first-in first-out buffer.

9. The method of claim 7, wherein the memory array includes buffers for buffering data sent to the hardware target and for buffering data received from the external processor.

10. The method of claim 7, wherein the target hardware comprises one of a digital signal processor, an application specific integrated circuit, and an integrated circuit.

11. The method of claim 7, wherein JTAG signals are sent by the FPGA to the hardware target without use of a controller that is external to the peripheral printed circuit board.

12. The method of claim 7, wherein the serial connector comprises one of a Universal Serial Bus (USB) connector, a Firewall (1394) connector, and an Ethernet connector.