Methods for shielding one or more circuit of a printed circuit board

• US 6,990,734 B2
• Filed: 10/02/2002
• Issued: 01/31/2006
• Est. Priority Date: 02/05/2001
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Underwood, Jeffrey A., Swirbel, Thomas J., Arledge, John K., Barreto, Joaquin
• Primary Examiner(s): Trinh, Minh
• Assistant Examiner(s): Nguyen, Donghai D.
• Application Number:
  US10/263,006
• Publication Number:
  US 20030024719A1
• Time in Patent Office: 1,217 Days
• Field of Search: 29830-834, 298/36, 298/37, 298/40, 298/41, 298/43, 298/52, 298/25, 298/46, 298/47, 174/35.R, 174/157, 174/250, 174255-277, 361/816, 361/818, 228/123.1, 228/180.21, 228/180.22, 228/248.1, 228/21
• US Class Current: 29/840
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0221 Coaxially shielded signal lines comprising a continuous shielding layer partially or wholly surrounding the signal lines
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0715 provided by an outer layer of PCB
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09809 Coaxial layout reduction of cross-talk, noise or interference by printed shielding conductors for shielding around a single via or around a group of vias H05K1/0222
• CPC Class Codes: H05K 2201/09972 Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
• CPC Class Codes: H05K 2201/09981 Metallised walls
• CPC Class Codes: H05K 2201/10553 Component over metal, i.e. metal plate in between bottom of component and surface of PCB
• CPC Class Codes: H05K 2201/10969 Metallic case or integral heatsink of component electrically connected to a pad on PCB
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 9/0039 Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing printed shielding conductors, ground planes or power planes for reduction of cross-talk or noise in printed circuits H05K1/0218
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

Methods for forming a metal shield on a printed circuit board (10) include depositing a first layer of metal (41) on a substrate (22) of the printed circuit board (10), depositing a first layer of dielectric material (42) on the first layer of metal (41), printing one or more circuits (21, 21′) on the first dielectric layer (42), depositing a second layer of dielectric material (43) over the one or more printed circuits (21, 21′), forming a trench-like opening (44) in the two layers of dielectric material (42, 43) surrounding the one or more printed circuits (21, 21′) so that the metal of the first layer (41) is exposed by the trench-like opening (44), depositing a second layer of metal (27) on the second layer of dielectric material (43) such that the second layer of metal (27) plates the trench-like opening (44) and makes electrical contact with the first metal layer (41).

Claims

1. A method for shielding one or more circuits of a printed circuit board, comprising the steps of:

depositing a first layer of metal on a substrate of the printed circuit board;

depositing a first layer of dielectric material on the first layer of metal;

printing more than one circuit on the first dielectric layer;

depositing a second dielectric layer over the first dielectric layer and over the more than one printed circuit thereon;

forming a trench opening in the two layers of dielectric material such that the trench opening surrounds the more than one printed circuit, and the metal of the first layer is exposed by the trench opening;

depositing a second layer of metal over the second layer of dielectric material such that the second layer of metal plates the trench opening and makes electrical contact with the first metal layer; and

providing one or more gaps in the metal deposited in the trench opening and routing a circuit trace therethrough.

2. The method of claim 1, including the step of creating a solder pad at each location where an electrical connection is to be made to the one or more printed circuits by removing a border of metal from the second layer of metal, the border surrounding each connection location, thereby leaving a portion of the second layer of metal at each connection location.

3. The method of claim 2, including the step of providing a microvia in each solder pad, the microvia extending through the second layer of dielectric material to the metal of the one or more printed circuits.

4. The method of claim 3, including the step of soldering an electrical component to one or more of the solder pads.

5. The method of claim 1, wherein the more than one printed circuit comprise at least two printed circuits, including the steps of providing a metal plated trench opening between two printed circuits and electrically connecting the metal plated trench opening surrounding the at least two printed circuits to the metal plated trench opening between the two printed circuits.