DC-coupled wideband signal converters

• US 6,992,611 B1
• Filed: 02/25/2005
• Issued: 01/31/2006
• Est. Priority Date: 02/25/2005
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Hand, James Jr., Lili, Tomas
• Primary Examiner(s): Nguyen, John B.
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US11/066,806
• Time in Patent Office: 340 Days
• Field of Search: 341/161, 341/120
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

Signal converters are provided that accurately process dc-coupled source signals in the presence of different predetermined voltage and current source requirements. Processing structures are described that satisfy these requirements while providing accurate control of common mode levels along a processing path and accurate reduction of converter offset errors.

Claims

1. A signal converter, comprising:

a differential amplifier having first and second bias ports, first and second input ports, and a differential output port that provides differential analog signals in response to signals at the input ports;

at least one converter stage that converts said differential analog signals to digital signals;

at least one adjustable voltage source;

a string of resistors coupled to said voltage source and defining first and second tap points with said second tap point coupled to said first input port; and

a controller configured to adjust said voltage source to provide predetermined voltage and current at said first tap point, to provide first and second bias voltages to said first and second bias ports to realize amplifier common-mode levels that conform to a voltage at said second tap point, and to apply an offset correction signal to said second input port to reduce offset errors in said digital signals.

2. The converter of claim 1, wherein said at least one adjustable voltage source comprises first and second adjustable voltage sources coupled to opposite ends of said string.

3. The converter of claim 1, wherein said string comprises three of said resistors with said first and second tap points defined by opposite ends of a middle one of said resistors.

4. The converter of claim 1, wherein said controller includes a digital processor that provides said offset correction signal in response to said digital signals.

5. The converter of claim 4, wherein said controller further includes:

first and second analog-to-digital converters that provide said first and second bias voltages;

a digital processor that derives a digital offset error in said digital signals; and

a third analog-to-digital converter that converts said digital offset error to said offset correction signal.

6. The converter of claim 1, wherein each of said adjustable voltage sources includes a digital rheostat that responds to said controller.

7. The converter of claim 1, further including an impedance matching circuit inserted between said amplifier and said converter.

8. A signal converter, comprising:

a differential amplifier having first and second bias ports, a first input port, and a differential output port that provides differential analog signals in response to signals at said input port;

an analog-to-digital converter that converts said differential analog signals to digital signals;

at least one adjustable voltage source;

a string of resistors coupled to said voltage source and defining first and second tap points with said second tap point coupled to said first input port; and

a controller configured to adjust said voltage source to provide predetermined voltage and current at said first tap point, and to provide first and second bias voltages to said first and second bias ports to realize amplifier common-mode levels that conform to a voltage at said second tap point.

9. The converter of claim 8, wherein:

said differential amplifier has a second input port and said differential output port provides differential analog signals in response to signals at said first and second input ports; and

said controller is configured to apply an offset correction signal to said second input port to reduce offset errors in said digital signals.

10. The converter of claim 9, wherein said controller further includes:

first and second analog-to-digital converters that provide said first and second bias voltages;

a digital processor that derives a digital offset error in said digital signals; and

a third analog-to-digital converter that converts said digital offset error to said offset correction signal.

11. The converter of claim 8, wherein said at least one adjustable voltage source comprises first and second adjustable voltage sources coupled to opposite ends of said string.

12. The converter of claim 8, wherein said string comprises three of said resistors with said first and second tap points defined by opposite ends of a middle one of said resistors.

13. The converter of claim 8, wherein each of said adjustable voltage sources includes a digital rheostat that responds to said controller.

14. The converter of claim 8, wherein said analog-to-digital converter includes pipelined converter stages.

15. The converter of claim 8, wherein said string is configured to present an impedance of substantially 50 ohms.

16. The converter of claim 8, further including an impedance matching circuit inserted between said amplifier and said converter.

17. A signal converter, comprising:

a differential amplifier having first and second bias ports, first and second input ports, and a differential output port that provides differential analog signals in response to signals at said input ports;

a converter system that converts said differential analog signals to digital signals;

at least one adjustable voltage source;

a string of resistors coupled to said voltage source and defining first and second tap points with said second tap point coupled to said first input port; and

a controller configured to adjust said voltage source to provide predetermined voltage and current at said first tap point, to provide first and second bias voltages to said first and second bias ports to realize amplifier common-mode levels that conform to a voltage at said second tap point, and to apply an offset correction signal to said second input port to reduce offset errors in said digital signals.

18. The converter of claim 17, wherein said converter system includes:

a plurality of serially connected converter stages in which at least one of said stages includes;

a) a comparator system that converts a respective portion of said differential analog signals to at least one corresponding digital bit of said digital signals; and

b) a residue generator that provides another portion of said differential analog signals to a subsequent one of said converter stages in the form of a residue signal which said generator generates in response to said respective portion and said corresponding digital bit.

19. The converter of claim 17, wherein said at least one voltage source comprises first and second adjustable voltage sources coupled to opposite ends of said string.

20. The converter of claim 17, wherein said controller includes a digital processor that provides said offset correction signal in response to said digital signals.