Memory unit having memory status indicator

• US 6,993,690 B1
• Filed: 07/23/1999
• Issued: 01/31/2006
• Est. Priority Date: 12/16/1998
• Status: Expired due to Term

• Current Assignee: Hagiwara Systems-Com Company Limited
• Original Assignee: Hagiwara Systems-Com Company Limited
• Inventors: Okamoto, Shinken
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US09/360,025
• Time in Patent Office: 2,384 Days
• Field of Search: 714/718, 714719-723, 714/185.33, 710/740, 324/210, 360/26, 360/47, 360/53, 365/200, 365/201, 365/185, 365/233, 365/232, 386/2, 386/47, 386/13, 386/85, 713/324, 713/340, 713/321
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A processing unit 12 that is provided in a memory unit 10 can transfer information that is stored in a corresponding address to a spare memory area and prohibit writing of information into the corresponding address when the number write operations to the respective addresses of flash memories 11-1 through 11-3 reaches a set number or when the error frequency in the information stored in the respective addresses reaches a set frequency. When the remaining capacity of a spare memory area reaches a set capacity, an indication lamp 14 may lit or a memory status signal may be transmitted to a processing unit 21 of a computer 20 and displayed on a display unit 30. The memory processing unit 12 may lit the indication lamp 14 when the number write operations to the respective addresses of flash memories 11-1 through 11-3 reaches a set number or when the error frequency in the information stored in the respective addresses reaches a set frequency.

Claims

1. A memory unit comprising:

a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage registers and wherein each of said data storage registers has an address, and wherein said spare memory area has a storage capacity;

a display; and

a processor, wherein said processor transfers data stored in each of said addresses of said main memory area to said spare memory area upon a number of write operations performed to a respective one of said addresses in said main memory reaching a predetermined value, and wherein said processor drives said display to display an operational status representative of remaining write operations of said flash memory upon said number of write operations performed to a respective one of said addresses in said main memory reaching a predetermined number.

2. The memory unit as in claim 1, wherein said processor compares said number of write operation performed with a plurality of different values of said predetermined values, wherein the comparison produces a plurality of different results, and wherein said processor drives said display to display different operational statuses of said flash memory in different manners dependent upon said plurality of different results.

3. A memory unit comprising:

a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage registers and wherein each of said data storage registers has an address, and wherein said spare memory area has a storage capacity;

a display; and

a processor, wherein said processor transfers data stored in each of said addresses of said main memory area to said spare memory area upon an error frequency within one of said plurality of data storage registers reaching a predetermined frequency, and wherein said processor drives said display to display an operational status representative of error frequency of said flash memory upon said error frequency reaching a predetermined frequency.

4. The memory unit of claim 3, wherein said processor compares said error frequency with a plurality of different values of said predetermined values, wherein the comparison produces a plurality of different results, and wherein said processor drives said display to display different operational statuses of said flash memory in different manners dependent upon said plurality of different results.

5. A memory unit comprising:

a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage registers and wherein each of said data storage registers has an address, and wherein said spare memory area has a storage capacity;

a display; and

a processor wherein said processor transfers data stored in each of said addresses of said main memory area to said spare memory area upon a number of write operations performed to a respective one of said addresses in said main memory reaching a predetermined value, and wherein said processor drives said display to display a normal operational status representative of remaining write operations of said flash memory when the number of write operations has not reached a first set value, a warning operational status representative of remaining write operations of said flash memory when the number of write operations has reached the first set value but not a second set value, and an extreme limit operational status representative of remaining write operations of said flash memory when the number of write operations has reached a second set value.

6. The memory unit as in claim 5, wherein a remaining amount of the storage capacity in said spare memory does not reach a first set remaining amount in the normal operational status, and the remaining amount of the storage capacity reaches the first set remaining amount but does not exceed the second set remaining amount in the warning operational status, and the remaining amount of the storage capacity exceeds a second set remaining amount in the extreme limit operational status, and the display is driven to display the normal operational status, the warning operational status and the extreme limit operational status in a distinguishable manner.

7. The memory unit as in claim 6, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed in different manners.

8. The memory unit as in claim 7, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using different colors.

9. The memory unit as in claim 8, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using blue, yellow and red, respectively.

10. The memory unit as in claim 5, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed in different manners.

11. The memory unit as in claim 10, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using different colors.

12. The memory unit as in claim 11, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using blue, yellow and red, respectively.

13. A flash memory unit comprising:

a flash memory area, wherein said flash memory area stores data and wherein said flash memory area has a limited useful life in storing said data;

a spare memory area having a data storage capacity;

a display; and

a processor, wherein said processor transfers the stored data of said flash memory area to said spare memory area upon said flash memory approaching said limited useful life, and wherein said processor drives said display to display an operational status representative of remaining useful life of said flash memory by displaying an amount of remaining data storage capacity in said spare memory, wherein the operational status of the display provides an indication as to whether replacement of said flash memory area is required.

14. The flash memory unit of claim 13 wherein the limited useful life is indicated by an increase in error frequency or by a finite number of read/write operations.

15. A flash memory unit utilizing error check code (ECC) comprising:

a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage addresses, and wherein said spare memory area includes a plurality of data storage addresses;

a display means; and

a processor, wherein said processor transfers data stored in each of said addresses of said main memory to one of said addresses of said spare memory area upon an error frequency of said one of said addresses in said main memory area reaching a predetermined value within the error frequency that a data error in said addresses of said main memory area can be corrected by said ECC stored in said flash memory, and

wherein said processor drives said display means to activate upon a remaining amount of storage capacity in said spare memory area reaching a predetermined value representative of error frequency and upon activation display an operational status of said flash memory.

16. The flash memory unit utilizing error check code (ECC) of claim 15, wherein said processor compares said error frequency with a plurality of different values of said predetermined values, and wherein said processor drives said display means to activate in different manners depending upon a plurality of comparison results and upon activation display different operational statuses of said flash memory.

17. The flash memory unit utilizing error check code (ECC) of claim 16, wherein a normal operational status, a warning operational status, and an extreme limit operational status of said flash memory are displayed in different manners.

18. A flash memory unit utilizing error check code (ECC) comprising:

a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage addresses, and wherein said spare memory area includes a plurality of data storage addresses;

a display means; and

a processor, wherein said processor transfers data stored in said main memory area to one of said addresses of said spare memory area upon the number of write operations performed to said addresses in said main memory area reaching a predetermined value representative of remaining write operations within possible number of write operations, and wherein said processor drives said display means to activate upon a remaining amount of storage capacity in said spare memory area reaching a predetermined value and upon activation display an operational status of said flash memory.

19. The flash memory unit utilizing error check code (ECC) of claim 18, wherein said processor compares said number of write operations to said addresses in said main memory area with a plurality of different values of said predetermined values, and wherein said processor drives said display means to activate in different manners depending upon a plurality of comparison results and upon activation display different operational statuses of said flash memory.

20. The flash memory utilizing Error Check Code (ECC) of claim 19, wherein a normal operational status, a warning operational status and an extreme limit operational status of said flash memory are displayed in different manners.