On-chip packet-based interconnections using repeaters/routers

• US 6,996,785 B1
• Filed: 04/25/2003
• Issued: 02/07/2006
• Est. Priority Date: 04/25/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Universal Network Machines Incorporated
• Inventors: Kizhepat, Govind, Kinaan, Omar M.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Doan, Nghia M.
• Application Number:
  US10/423,499
• Time in Patent Office: 1,019 Days
• Field of Search: 716 1- 10, 712 12- 43, 711119-212
• US Class Current: 716/138
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which do not depend on establishing clock-cycle sequenced handshakes. On-chip repeaters including one or more register stages are used to segment the agent-shared resource interconnects into multiple segments, each shorter than a single-clock-cycle pathlength. The interconnects of multiple closely-spaced agents can be routed to the shared resource through an on-chip router having a single routed connection to the shared resource, for reducing the floorplan space taken by interconnects. The packet-based communications protocols do not require redesigning the agents or memory controller to make protocol changes accounting for the clock cycles inserted by repeaters and/or routers. Each agent can include a port register for storing a corresponding port number of the shared resource, to facilitate the host-programmable assignment of agents to shared resource ports.

Claims

1. A synchronous apparatus integrated on a chip, comprising:

a shared functional block integrated on the chip;

a plurality of agent functional blocks integrated on the chip and connected to the shared functional block through a corresponding plurality of unidirectional packet buses, wherein a communications protocol between the shared functional block and an agent functional block is independent of a number of clock cycles defining a signal traveltime over a packet bus connecting the agent functional block and the shared functional block; and

a repeater integrated on the chip, comprising a register positioned to segment the packet bus connecting the agent functional block and the shared functional block, for receiving a packet from a first unit selected from the agent functional block and the shared functional block on a first clock cycle, and transmitting the packet to a second unit selected from the agent functional block and the shared functional block on a second clock cycle subsequent to the first clock cycle.

2. The apparatus of claim 1, wherein the shared functional block comprises a memory controller, and each of the agent functional blocks comprises a memory client capable of transmitting memory read and memory write commands to the memory controller through the repeater.

3. The apparatus of claim 1, wherein the repeater comprises a router connecting at least two agent functional blocks to the shared functional block, the router being connected to the shared functional block over a shared, routed unidirectional packet bus, the router comprising arbitration logic for arbitrating a transmission of packets from the at least two agent functional blocks to the shared functional block.

4. The apparatus of claim 3, wherein the router comprises:

an input register stage comprising a plurality of registers each connected to one of the at least two agent functional blocks;

arbitration logic connected to the input register stage, for selecting for transmission on a clock cycle a single packet corresponding to one of the plurality of registers of the input register stage, and for adding to the single packet a sender tag identifying a sender of the single packet; and

an output register stage comprising an output register connected to the shared functional block, for receiving the single packet from the arbitration logic.

5. The apparatus of claim 1, further comprising a router connecting at least two agent functional blocks to the shared functional block, the router being connected to the shared functional block over a shared, routed unidirectional packet bus, the router comprising arbitration logic for arbitrating a transmission of packets from the at least two agent functional blocks to the shared functional block.

6. The apparatus of claim 1, wherein:

a first physical connection distance between the repeater and a first agent functional block over the packet bus does not exceed a single-clock-cycle length; and

a second physical connection distance between the shared functional block and the first agent functional block over the packet bus exceeds the single-clock-cycle length.

7. The apparatus of claim 1, wherein the repeater comprises clock gating logic connected to the register, for gating a clock signal to the register selectively if the packet presently stored in the register is a no-operation packet and an incoming packet is no-operation packet.

8. The apparatus of claim 1, wherein the second clock cycle immediately follows the first clock cycle.

9. The apparatus of claim 1, wherein the second clock cycle is two clock cycles later than the first clock cycle.

10. The apparatus of claim 1, further comprising an additional repeater integrated on the chip, comprising an additional register positioned to segment the packet bus connecting the agent functional block and the shared functional block.

11. The apparatus of claim 1, wherein the repeater is a single-agent repeater.

12. A synchronous apparatus integrated on a chip, comprising:

a first functional block integrated on the chip;

a second functional block integrated on the chip and connected to the first functional block through a unidirectional packet bus, wherein a communications protocol between the first functional block and the second functional block is independent of a number of clock cycles defining a signal traveltime over the packet bus; and

a repeater integrated on the chip, comprising a register positioned to segment the packet bus, for receiving a packet from the first functional block on a first clock cycle, and transmitting the packet to the second functional block on a second clock cycle subsequent to the first clock cycle.

13. The apparatus of claim 12, wherein the first functional block comprises a memory controller, and the second functional block comprises a memory client capable of transmitting memory read and memory write commands to the memory controller through the repeater.

14. The apparatus of claim 12, wherein the repeater comprises a router connecting a third functional block integrated on the chip and the second functional block to the first functional block, the router being connected to the first functional block over a first, routed unidirectional packet bus, the router comprising arbitration logic for arbitrating a transmission of packets from the second functional block and the third functional block to the first functional block.

15. The apparatus of claim 14, wherein the router comprises:

an input register stage comprising a first register connected to the second functional block and a second register connected to the third functional block;

arbitration logic connected to the input register stage, for selecting for transmission on a clock cycle a single packet corresponding to one of the first register and the second register, and adding to the single packet a sender tag identifying a sender of the single packet; and

an output register stage comprising a third register connected to the first functional block, for receiving the single packet from the arbitration logic.

16. The apparatus of claim 12, further comprising a router connecting a third functional block integrated on the chip and the second functional block to the first functional block, the router being connected to the first functional block over a first, routed unidirectional packet bus, the router comprising arbitration logic for arbitrating a transmission of packets from the second functional block and the third functional block to the first functional block.

17. The apparatus of claim 12, wherein:

a first physical connection distance between the repeater and the first functional block over the packet bus does not exceed a single-clock-cycle length; and

a second physical connection distance between the first functional block and the second functional block over the packet bus exceeds the single-clock-cycle length.

18. The apparatus of claim 12, wherein the repeater comprises clock gating logic connected to the register, for gating a clock signal to the register selectively if the packet presently stored in the register is a no-operation packet and an incoming packet is no-operation packet.

19. The apparatus of claim 12, wherein the second clock cycle immediately follows the first clock cycle.

20. The apparatus of claim 12, wherein the second clock cycle is two clock cycles later than the first clock cycle.

21. The apparatus of claim 12, further comprising an additional repeater integrated on the chip, comprising an additional register positioned to segment the packet bus connecting the first agent functional block and the second agent functional block.

22. The apparatus of claim 12, wherein the repeater is a single-agent repeater.

23. A synchronous apparatus integrated on a chip, comprising:

shared means integrated on the chip;

plural agent means integrated on the chip and connected to the shared means through a corresponding plurality of unidirectional communications means, wherein a communications protocol between the shared means and an agent means is independent of a number of clock cycles defining a signal traveltime over a communications means connecting the agent means and the shared means; and

repeater means integrated on the chip, comprising a register positioned to segment the communications means between the agent means and the shared means, for receiving a packet from the shared means or the agent means on a first clock cycle, and transmitting the packet to the shared means or the agent means on a second clock cycle subsequent to the first clock cycle.

24. A synchronous apparatus integrated on a chip, comprising:

a memory controller integrated on the chip;

a plurality of memory clients integrated on the chip and connected to the memory controller through a corresponding plurality of unidirectional packet buses, wherein a communications protocol between the memory controller and a memory client is independent of a number of clock cycles defining a signal traveltime over a packet bus connecting the memory client and the memory controller; and

a repeater integrated on the chip, comprising a register positioned to segment the packet from a first unit selected from the memory client and the memory controller bus between the memory client and the memory controller, for receiving a packet on a first clock cycle, and transmitting the packet to a second unit selected from the memory client and the memory controller on a second clock cycle subsequent to the first clock cycle.

25. An on-chip data communications method comprising:

transmitting a data packet from a first functional block integrated on a chip over a first segment of a unidirectional packet bus;

receiving the data packet at a repeater connected to the first segment;

storing the data packet in a register of the repeater on a first clock cycle;

transmitting the data packet from the repeater over a second segment of the unidirectional packet bus on a second clock cycle subsequent to the first clock cycle; and

receiving the data packet at a second functional block connected to the second segment, wherein a communications protocol between the first functional block and the second functional block is independent of a number of clock cycles defining a signal traveltime over the packet bus.

26. A chip design method comprising:

establishing an integrated circuit description including

a description of a first functional block integrated on the chip, and

a description of a second functional block integrated on the chip and connected to the first functional block through a unidirectional packet bus, wherein a communications protocol between the first functional block and the second functional block is independent of a number of clock cycles defining a signal traveltime over the packet bus; and

inserting into the integrated circuit description a description of a repeater integrated on the chip, the repeater comprising a register positioned to segment the packet bus, for receiving a packet from the first functional block on a first clock cycle, and transmitting the packet to the second functional block on a second clock cycle subsequent to the first clock cycle.