System and method for testing memory

• US 7,000,159 B2
• Filed: 03/10/2003
• Issued: 02/14/2006
• Est. Priority Date: 03/10/2003
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Alexander, Marc D., Stern, Jonathan T.
• Primary Examiner(s): Ton, David
• Application Number:
  US10/385,228
• Publication Number:
  US 20040181716A1
• Time in Patent Office: 1,072 Days
• Field of Search: 714/9, 714/36, 714/719, 714/718, 714/14, 713/2, 711/153
• US Class Current: 714/718
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A system and method for reducing the amount of time for a boot operation is provided that includes a test management module that divides the memory into multiple test blocks and then selects a limited number of test blocks to test during a boot operation, thereby decreasing the overall amount of memory test time.

Claims

1. An information handling system comprising:

a BIOS having a test management module;

a memory;

the BIOS in communication with the memory and operable to test the memory;

the test management module operable to;

divide the memory into a base memory block and a plurality of memory test blocks; and

test the base memory block and test a selected memory test block during a boot operation.

2. The information handling system of claim 1 wherein the memory comprises system RAM.

3. The information handling system of claim 1 further comprising the BIOS operable to perform data testing and address testing on the memory.

4. The information handling system of claim 1 further comprising the management module operable to:

determine the total amount of memory;

designate the size of the base memory block as a selected first fraction of total memory; and

designate the size of each memory test block as a selected second fraction of total memory.

5. The information handling system of claim 4 wherein the base memory is approximately one-tenth of the total memory.

6. The information handling system of claim 4 wherein the base memory is approximately one-sixteenth of the total memory.

7. The information handling system of claim 1 further comprising the test management module operable to initiate a test of the complete memory in response to a trigger condition.

8. The information handling system of claim 7 further comprising the trigger condition selected from the group consisting of:

a chassis intrusion, a change in memory serial number, a change total memory, a detected thermal incident, a lapse of a selected period, and a lapse of a selected number of consecutive cold boots without a complete memory test.

9. The information handling system of claim 7 further comprising the trigger condition comprising a first cold boot.

10. The information handling system of claim 1 further comprising:

the test management module operable to divide the memory into the base memory and a series of memory test blocks;

the test management module further operable to select the next consecutive memory test block for testing during each boot operation.

11. The information handling system of claim 10 wherein the boot operation comprises a cold boot.

12. A test management module for an information handling system comprising:

a test block assignment module operable to divide a memory into a base memory block and a plurality of sequential memory test blocks;

a test block pointer operable to record the most recently tested memory test block;

a trigger condition indicator operable to determine whether a trigger condition exists; and

the test management module operable to test the base memory block and a selected memory test block during a boot operation.

13. The test management module of claim 12 further comprising the test management module operable to test all memory blocks where the trigger condition indicator determines that a trigger condition exists.

14. The test management module of claim 12 further comprising the test management module operable to test the next sequential test block where the trigger condition indicator determines that no trigger condition exists.

15. The test management module of claim 12 further comprising the trigger condition selected from the group consisting of:

a first boot, a chassis intrusion, a change in memory serial number, a change total memory, a detected thermal incident, a lapse of a selected period and a lapse of a selected number of consecutive cold boots without a complete memory test.

16. A method to decrease boot time in a cold boot of an information handling system, the method comprising:

dividing a memory into a base memory block and a plurality of memory test blocks;

selecting a memory test block for testing;

testing the base memory block;

testing the memory test block.

17. The method of claim 16 further comprising:

determining whether a trigger condition exists; and

reading a test block pointer identifying next test memory block to test.

18. The method of claim 17 further comprising testing all memory test blocks and setting the pointer to the first memory test block if a trigger condition is determined.

19. The method of claim 17, further comprising testing the memory test block indicated by the pointer and setting the pointer to the next sequential memory test block.

20. The method of claim 17 further comprising the trigger condition selected from the group consisting of:

a chassis intrusion, a change in memory serial number, a change total memory, a detected thermal incident, a lapse of a selected period and a lapse of a selected number of consecutive cold boots without a complete memory test.