Image sensor with motion artifact supression and anti-blooming

• US 7,002,626 B2
• Filed: 10/26/2001
• Issued: 02/21/2006
• Est. Priority Date: 01/06/1999
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yang, Guang, Pain, Bedabrata, Yadid-Pecht, Orly, Wrigley, Chris
• Primary Examiner(s): Tran, Thai
• Assistant Examiner(s): Vieaux, Gary C.
• Application Number:
  US09/999,232
• Publication Number:
  US 20020036300A1
• Time in Patent Office: 1,579 Days
• Field of Search: 348/241, 348/314, 348/302, 348/308, 348/299, 257/215, 257/184, 257/223, 257/230, 257/229, 257/291, 438/79
• US Class Current: 348/241
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/623 by evacuation via the output or reset lines
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.

Claims

1. An image sensor comprising:

a plurality of pixels on a semiconductor substrate, wherein each pixel includes;

a photoactive region in the semiconductor substrate;

a sense node;

a first electrode disposed near a surface of the semiconductor substrate, wherein, during operation, a bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node;

a power supply node; and

a second electrode disposed near the surface of the semiconductor substrate, wherein, during operation, a bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node; and

a controller that, during operation, causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photo-charges are transferred to the sense node during a charge transfer period, and additional photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node, wherein the transfer of the accumulated photocharges to the sense node is achieved by raising a bias voltage on the first electrode and lowering a bias voltage on the second electrode.

2. The image sensor of claim 1 wherein the integration period of the pixels occurs at substantially the same time.

3. The image sensor of claim 1 wherein, during operation, the controller provides a bias signal to the second electrode so that excess photocharges generated in the photoactive region are transferred to the power supply node during the pixel integration period.

4. The image sensor of claim 1 wherein the plurality of pixels include photogate-type pixels.

5. The image sensor of claim 1 wherein the plurality of pixels include photodiode-type pixels.

6. The image sensor of claim 1 wherein each pixel further includes a reset gate, wherein, during operation, the controller provides a bias signal to the reset gate to cause charge in the pixel'"'"'s sense node to be transferred to a power supply node.

7. The image sensor of claim 1 the pixels are active pixels.

8. The image sensor of claim 1 wherein each pixel includes an amplifier and a pixel selection switch.

9. An image sensor comprising:

an array of pixels on a semiconductor substrate, wherein each pixel includes;

a photoactive region in the semiconductor substrate;

a sense node;

a power supply node; and

first and second transfer gates disposed in proximity to the surface of the semiconductor substrate; and

a controller that, during operation, causes bias signals to be provided to the electrodes to operate the pixels in at least three modes including a first mode in which photocharges generated in the photoactive region of a pixel are accumulated in the pixel'"'"'s photoactive region, a second mode in which the accumulated photocharges are transferred to the pixel'"'"'s sense node via the pixel'"'"'s first transfer gate, and a third mode in which additional photocharges generated in the pixel'"'"'s photoactive region are transferred to the pixel'"'"'s power supply node via the pixel'"'"'s second transfer gate without passing through the pixel'"'"'s sense node, wherein the transfer of the accumulated photocharges to the sense node is achieved by raising a bias voltage on the first transfer gate and lowering a bias voltage on the second transfer gate.

10. The image sensor of claim 9 wherein each pixel is identified by a row and column in the array and includes a row selection switch that is selectively enabled by the controller to read out a signal stored by the pixel'"'"'s sense node.

11. The image sensor of claim 10 wherein, during operation, the controller controls the row selection switches to read out the rows of pixels sequentially, one row of pixels at a time.

12. The image sensor of claim 9 in which each pixel is operated in the first mode at substantially the same time.

13. The image sensor of claim 12 in which each pixel is operated in the second mode at substantially the same time.