Analog to digital converter with internal data storage

• US 7,002,628 B1
• Filed: 03/30/1999
• Issued: 02/21/2006
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Panicacci, Roger
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): TRAN, NHAN T
• Application Number:
  US09/281,358
• Time in Patent Office: 2,520 Days
• Field of Search: 348294-324, 348/222.1, 348/241, 378/58.8, 378/98.8, 341/126, 341/155, 341/141, 250/208.1, 257291-293
• US Class Current: 348/307
• CPC Class Codes: H03M 1/1023 Offset correction H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/403 using switched capacitors

Abstract

An analog-to-digital converter in an active pixel sensor array includes on board memory elements for storing results. The stored results can be read out in a different order than the order in which they were converted.

Claims

1. An active pixel sensor device, comprising:

an array of pixels, arranged in logical units, wherein each pixel comprises a photosensor element, an in-pixel buffer element, and an in-pixel selector element;

a plurality of analog-to-digital converters, formed on the same substrate as said pixel sensor array, and each associated with N logical units of the pixel sensor array, each of said N logical units having including a plurality of pixels, each of said plurality of analog-to-digital converters comprising;

a plurality of storage elements; and

an analog-to-digital (ADC) portion, said ADC portion for receiving an analog signal from one of said pixel sensors of an associated logical unit when a selector element associated with said one pixel is enabled, and for converting said analog signal to a converted digital value, said ADC portion storing said converted value into one of said plurality of storage elements; and

a readout controller for controlling readout of information from the photosensor elements by controlling each of said analog-to-digital converters to;

convert first information from a first line of the array and store said first information in one of said plurality of storage elements;

after said convert and store of said first information, convert second information from a second line of the array and store said second information in another one of said plurality of storage elements; and

read out said first and second information from said plurality of storage elements in a desired order;

wherein N is at least two.

2. A sensor as in claim 1, wherein said logical units are lines of the array including either columns of the array or rows of the array.

3. A device as in claim 2, wherein said analog-to-digital converters are associated with at least two adjacent lines of the array.

7. The device of claim 1, wherein each pixel is a CMOS pixel.

4. A method of operating a pixel sensor array, comprising:

obtaining a pixel sensor array of photosensitive elements, each having a photosensitive element in a pixel, a buffer in said pixel associated with said photosensitive element, and a selector transistor in said pixel which is enabled to allow a signal from said pixel to pass, and disabled to block the signal from passing;

connecting a plurality of said outputs of said selector transistors to one another, to form a plurality of logical units, each logical unit formed by a plurality of said output transistors which are connected to one another;

receiving, in each of a plurality of A/D converter units each comprising a plurality of first storage unit, a plurality of second storage units, and an analog-to-digital conversion (ADC) portion, a respective plurality of signals from a respective plurality of first logical units, and A/D converting said respective plurality of signals into a respective plurality of converted digital values and storing said respective plurality of converted digital values information in a respective one of said plurality of first storage units;

receiving, in said plurality of A/D converter units, a respective of signals from a respective plurality of second logical units, adjacent to said first logical units, and A/D converting said respective plurality of signals into a respective plurality of converted digital values and storing said respective plurality of converted digital values in a respective one of said plurality of second storage units; and

reading out said information from said A/D conversion unit in a different order than an order in which the information was converted.

5. A method as in claim 4, wherein said different order is in a serial order.

6. A method as in claim 4, wherein said units are linear units which are one of rows and columns, and said different order include a first different order which skips lines between conversions, and a second different order which is a complete order.