In-situ nitride/oxynitride processing with reduced deposition surface pattern sensitivity

• US 7,009,226 B1
• Filed: 07/12/2004
• Issued: 03/07/2006
• Est. Priority Date: 07/12/2004
• Status: Active Grant

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sun, Sey-Ping
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US10/887,836
• Time in Patent Office: 603 Days
• Field of Search: 257/192, 257/616, 257/649, 257/900
• US Class Current: 257/192
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Carrier mobility in transistor channel regions is increased by depositing a conformal stressed liner. Embodiments include forming a silicon oxynitride layer on the stressed liner to reduce or eliminate deposition surface pattern sensitivity during gap filling, and in-situ SACVD of silicon oxide gap fill directly on the stressed liner with reduced pattern sensitivity. Embodiments also include the use of Si—Ge substrates.

Claims

1. A semiconductor device comprising:

a substrate;

a plurality of transistors formed on the substrate, each transistor comprising source/drain regions and a gate electrode, having an upper and side surfaces, over the substrate with a gate dielectric layer therebetween, the gate electrodes being separated by a gap;

a conformal stressed nitride liner over the upper and side surfaces of the gate electrodes and over the source/drain regions; and

a dielectric layer over the transistors and filling the gaps between the gate electrodes.

2. The semiconductor device according to claim 1, further comprising a conformal silicon oxynitride layer on the stressed nitride liner, and the dielectric layer on the conformal silicon oxynitride layer filling the gaps.

3. The semiconductor device according to claim 1, wherein the substrate comprises a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si—

Ge).

4. The semiconductor device according to claim 3, wherein:

the transistor is a P-channel transistor; and

the stressed nitride liner exhibits high compressive stress.

5. The semiconductor device according to claim 3, wherein:

the transistor is an N-channel transistor; and

the stressed nitride liner exhibits high tensile stress.

6. The semiconductor device according to claim 1, further comprising:

dielectric sidewall spacers on side surfaces of the gate electrodes; and

a layer of metal silicide on the upper surface of the gate electrodes and on the source/drain regions, wherein the stressed nitride liner is on the sidewall spacers and metal silicide layers.

7. The semiconductor device according to claim 6, wherein:

the sidewall spacers comprise an oxide liner on the side surfaces of the gate electrode and on an upper surface portion of the substrate, and a nitride layer on the oxide liner.

8. The semiconductor device according to claim 1, wherein:

the stressed nitride liner comprises silicon nitride and has a thickness of about 200 Å

to about 1000 Å

; and

the silicon oxynitride layer has a thickness of about 20 Å

to about 40 Å

.

9. The semiconductor device according to claim 8, wherein the dielectric layer comprises silicon oxide and has a thickness of about 6,500 Å

to about 7,500 Å

.