Active matrix liquid crystal display having a thin film transistor over which alignment of liquid crystal molecules does not change

• US 7,009,673 B2
• Filed: 09/08/2003
• Issued: 03/07/2006
• Est. Priority Date: 07/17/2000
• Status: Expired due to Term

• Current Assignee: Vista Peak Ventures LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: NEC LCD Technologies Limited (NEC Corporation)
• Inventors: Nishida, Shinichi, Matsumoto, Kimikazu
• Primary Examiner(s): NGO, HUYEN LE
• Application Number:
  US10/656,138
• Publication Number:
  US 20040046903A1
• Time in Patent Office: 911 Days
• Field of Search: 349/141, 349/123, 349/43
• US Class Current: 349/141
• CPC Class Codes: G02F 1/133784 by rubbing
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

In an active matrix liquid crystal display device, a drain and source of a TFT element for controlling power supply to a pixel electrode, are arranged so that an alignment direction of liquid crystal molecules over the source and drain does not change, thereby preventing formation of ghost images in the display. In one embodiment, an electric field generated between the source and drain is parallel to an initial non-zero alignment angle of the molecules.

Claims

1. An active matrix liquid crystal display, comprising:

a pair of substrates with a liquid crystal layer between said substrates;

a pixel electrode and a common electrode having a common longitudinal axis and that are arranged and adapted to generate an electric field parallel to said substrates in said liquid crystal layer, said liquid crystal layer having a non-zero initial alignment angle relative to the common longitudinal axis; and

a thin film transistor having a source electrode and a drain electrode adjacent to a first part of said liquid crystal layer, said source and drain electrodes being arranged and adapted so that an electric field generated between said source and drain electrodes is one of substantially parallel to and perpendicular to the non-zero initial alignment angle, whereby an alignment of the first part of said liquid crystal layer does not change when an electric field is generated between said source and drain electrodes.

2. The display of claim 1, wherein said source and drain electrodes are arranged and adapted so that an electric field generated between said source and drain electrodes is substantially parallel to the non-zero initial alignment angle, and wherein said source and drain electrodes have facing edges that are parallel to each other and perpendicular to the non-zero-initial alignment angle.

3. The display of claim 2, wherein said source and drain electrodes each have opposing sides that are parallel to each other and parallel to the non-zero-initial alignment angle.

4. The display of claim 2, further comprising an island of amorphous silicon adjacent to said source and drain electrodes, wherein said island has opposing sides that are parallel to each other and perpendicular to the non-zero-initial alignment angle.

5. The display of claim 1, wherein said source and drain electrodes are arranged and adapted so that an electric field generated between said source and drain electrodes is substantially perpendicular to the non-zero initial alignment angle, and wherein said source and drain electrodes have facing edges that are parallel to each other and parallel to the non-zero-initial alignment angle.

6. The display of claim 1, wherein said source and drain electrodes are arranged and adapted so that an electric field generated between said source and drain electrodes is substantially parallel to the non-zero initial alignment angle, and further comprising an island of amorphous silicon adjacent to said source and drain electrodes, wherein said island has opposing sides that are parallel to each other and perpendicular to the non-zero-initial alignment angle.

7. The display of claim 1, wherein said display comprises an array of parallel data lines, and wherein the common longitudinal axis of said pixel and common electrodes is parallel to the data lines.

8. The display of claim 1, wherein said display comprises an array of parallel data lines, and wherein the common longitudinal axis of said pixel and common electrodes is transverse to the data lines.