Switched capacitor circuit with reduced common-mode variations
DC CAFCFirst Claim
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1. A circuit with a common-mode dual output comprising:
- a common-mode circuit with an output portion;
a common-mode corrector circuit connected to alternate the states of said output portion between an average output level and a desired common-mode level, the difference between the average and desired levels being proportional to a signal offset level; and
an error correcting circuit connected to said common-mode corrector circuit to adjust the signal offset level;
wherein said common-mode corrector circuit further includes;
a common-mode voltage terminal connected to said output portion through a first pair of switches, said first pair of switches being responsive to alternating clock cycles which alternate the states of said output portion;
a bias terminal providing a bias level, said bias terminal being connected to a first control terminal in said common-mode circuit through a second pair of switches, said second pair of switches being responsive to the alternating clock cycles;
a precharging capacitor which stores the difference between the desired common-mode level and the bias level during a first clock cycle in the alternating clock cycles; and
a common-mode capacitor which stores the average output level during the first clock cycle, said common-mode capacitor and said precharging capacitor being connected in parallel during a second clock cycle in the alternating clock cycles.
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Abstract
A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.
33 Citations
29 Claims
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1. A circuit with a common-mode dual output comprising:
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a common-mode circuit with an output portion; a common-mode corrector circuit connected to alternate the states of said output portion between an average output level and a desired common-mode level, the difference between the average and desired levels being proportional to a signal offset level; and an error correcting circuit connected to said common-mode corrector circuit to adjust the signal offset level; wherein said common-mode corrector circuit further includes; a common-mode voltage terminal connected to said output portion through a first pair of switches, said first pair of switches being responsive to alternating clock cycles which alternate the states of said output portion; a bias terminal providing a bias level, said bias terminal being connected to a first control terminal in said common-mode circuit through a second pair of switches, said second pair of switches being responsive to the alternating clock cycles; a precharging capacitor which stores the difference between the desired common-mode level and the bias level during a first clock cycle in the alternating clock cycles; and a common-mode capacitor which stores the average output level during the first clock cycle, said common-mode capacitor and said precharging capacitor being connected in parallel during a second clock cycle in the alternating clock cycles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit, comprising:
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a differential amplifier circuit with an output portion and a current sinking portion, said output portion including dual outputs which provide an average output level; a common-mode feedback circuit coupled to said output portion, said feedback circuit providing a desired common-mode level in a first operational mode and generating a feedback signal proportional to the difference between the average output level and the desired common-mode level in a second operational mode, the feedback signal being coupled to said current sinking portion; and an impedance matching circuit connected to said feedback circuit to adjust the feedback signal; wherein the desired common-mode signal is provided to a precharging capacitor in the first operational mode, said precharging capacitor including a terminal coupled to said impedance matching circuit. - View Dependent Claims (12, 13, 14, 15, 16, 17, 29)
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18. A switched capacitor amplifier which provides an output signal in response to an input signal and corrects the average output level of the output signal in accordance with a desired common-mode level, said amplifier comprising:
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a differential amplifier with an output portion and a current sinking portion, said output portion providing the output signal; a switched capacitor common-mode feedback circuit coupled between said output portion and said current sinking portion, said feedback circuit being configured to alternate the states of said output portion between the average output level on a precharging capacitor and the desired common-mode level on a commonmode feedback capacitor in response to alternating clock cycles, the difference between the average and desired levels being proportional to a signal offset level; an impedance matching circuit coupled to said feedback circuit to adjust the signal offset level, said impedance matching circuit including a charge balancing switch configured to reduce feedthrough between said differential amplifier and said feedback circuit. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification