Method and apparatus for multithreaded processing of data in a programmable graphics processor

• US 7,015,913 B1
• Filed: 06/27/2003
• Issued: 03/21/2006
• Est. Priority Date: 06/27/2003
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Bastos, Rui M., Lindholm, John Erik, Zatz, Harold Robert Feldman
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US10/608,346
• Time in Patent Office: 998 Days
• Field of Search: 345/501, 345/504, 345/520, 345/522, 345/420, 345/423, 345/503, 345/519, 345/506, 345/543, 345/557, 709/208, 709/231, 712/23, 712/28, 712 31- 32, 718/102, 718/104
• US Class Current: 345/501
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A graphics processor and method for executing a graphics program as a plurality of threads where each sample to be processed by the program is assigned to a thread. Although threads share processing resources within the programmable graphics processor, the execution of each thread can proceed independent of any other threads. For example, instructions in a second thread are scheduled for execution while execution of instructions in a first thread are stalled waiting for source data. Consequently, a first received sample (assigned to the first thread) may be processed after a second received sample (assigned to the second thread). A benefit of independently executing each thread is improved performance because a stalled thread does not prevent the execution of other threads.

Claims

1. A method of rendering a scene using a graphics processor comprising:

configuring a multithreaded processing unit within the graphics processor to enable processing of samples independent of an order in which the samples are received;

processing the samples independent of the order in which the samples are received by the multithreaded processing unit to render at least a portion of the scene; and

configuring the multithreaded processing unit to disable processing of samples independent of an order in which the samples are received to minimize visual artifacts in the rendered scene by preventing the occurrence of position hazards.

2. The method of claim 1, further comprising:

processing a portion of the samples in the order in which the samples are received by the multithreaded processing unit.

3. The method of claim 2, wherein the portion of the samples includes samples within intersecting objects.

4. The method of claim 2, wherein the portion of the samples includes samples within coincident objects.

33. A method as claimed in claim 1 wherein each thread of the multithreaded processing unit may be separately configured to selectively enable or disable processing of samples independent of the order in which the samples are received.

5. A graphics processor for multithreaded execution of program instructions comprising:

at least one multithreaded processing unit configured to receive samples in a first order to be processed by program instructions associated with at least one thread including;

a scheduler configured to receive the program instructions, determine availability of source data, and schedule the program instructions for execution to process the samples in a second order independent of the first order;

a resource tracking unit configured to track the availability of the source data; and

a dispatcher configured to output the program instructions in the second order to be executed by the at least one multithreaded processing unit.

6. The graphics processor of claim 5, wherein the samples include at least one of vertices, primitives, surfaces, fragments and pixels.

7. The graphics processor of claim 5, further comprising a thread control buffer configured to store program counters, each program counter associated with one of the at least one thread.

8. The graphics processor of claim 5, further comprising an instruction cache configured to store the program instructions.

9. The graphics processor of claim 5, wherein the scheduler is configured to schedule the program instructions for execution to process the samples in a second order where the second order is the same as the first order.

10. The graphics processor of claim 5, wherein the scheduler is configured to schedule the program instructions for execution after ordering the program instructions.

11. The graphics processor of claim 10, wherein the ordering is based on the number of cycles each of the program instructions has been in an instruction window unit.

12. The graphics processor of claim 5, wherein the scheduler is configured to determine availability of computation resources within the at least one multithreaded processing unit.

13. The graphics processor of claim 12, wherein the resource tracking unit is configured to track the availability of the computation resources.

14. The graphics processor of claim 5, wherein the at least one multithreaded processing unit is configured to allocate storage resources to the at least one thread.

15. The graphics processor of claim 5, wherein the at least one multithreaded processing unit is configured to maintain thread state data for the at least one thread.

16. The graphics processor of claim 15, wherein a portion of the thread state data indicates whether the thread is either assigned to a sample or is available to be assigned to a sample.

17. A computing system comprising:

a host processor;

a host memory, the host memory storing programs for the host processor;

a system interface configured to interface with the host processor; and

a graphics processor for multithreaded execution of program instructions Including;

at least one multithreaded processing unit configured to receive samples in a first order to be processed by program instructions associated with at least one thread including;

a scheduler configured to receive the program instructions, determine availability of source data, and schedule the program instructions for execution in a second order independent of the first order;

a resource tracking unit configured to track the availability of the source data; and

a dispatcher configured to output the program instructions in the second order to be executed by the at least one multithreaded processing unit.

18. The computing system of claim 17, wherein the host memory is configured to interface with the system interface.

19. The computing system of claim 17, wherein the host memory is configured to directly interface with the host processor.

20. A method of processing a first program instruction associated with a first thread and a second program instruction associated with a second thread comprising:

receiving a first sample to be processed by the first program instruction associated with the first thread before receiving a second sample to be processed by the second program instruction associated with the second thread;

determining that first source data required to process the first program instruction are not available;

determining that second source data required to process the second program instruction are available; and

dispatching the second program instruction to process the second sample in an execution unit prior to dispatching the first program instruction to process the first sample in the execution unit.

21. The method of claim 20, further comprising determining that a position hazard does not exist between a position of the first sample and a position of any other sample being processed by a program instruction in the execution unit.

22. The method of claim 21, further comprising, prior to the determining that a position hazard does not exist, disabling processing of samples independent of an order in which the samples are received using a programmable mode.

23. The method of claim 20, further comprising determining that a position hazard does not exist between a position of the second sample and a position of any other sample being processed by a program instruction in the execution unit.

24. The method of claim 20, further comprising:

retaining as state information the position of the first sample received to be processed by the first program instruction associated with the first thread; and

updating the state information when the first thread has completed execution.

25. The method of claim 20, further comprising:

retaining as state information the position of the second sample received to be processed by the second program instruction associated with the second thread; and

updating the state information when the second thread has completed execution.

26. The method of claim 20, further comprising allocating storage resources to the second thread.

27. The method of claim 20, further comprising allocating storage resources to the first thread.

28. A method of using a function call to configure a graphics processor comprising:

detecting that a multithreaded processing unit within the graphics processor supports processing of samples independent of an order in which the samples are received for at least one sample type;

issuing a function call to configure the multithreaded processing unit to enable processing of samples independent of an order in which the samples are received for the at least one sample type; and

ending the function call during rendering of an output image to disable processing of samples independent of the order In which they are received to prevent image artifacts due to position hazards.

29. A method as claimed in claim 28 wherein the multithreaded processing unit is configured to process several output pixel locations distributed across the output image.

30. A method as claimed in claim 28 wherein the multithreaded processing unit is configured to process several adjacent output pixel locations within the output image.

31. A method as claimed in claim 28 wherein the multithreaded processing unit is configured to process regions of four adjacent pixels arranged in a square with the squares located within the output image.

32. A method as claimed in claim 28 wherein a separate one of the function calls may be issued for each of the multithreaded processing unit.