Dynamic power control in integrated circuits

• US 7,032,117 B2
• Filed: 12/19/2002
• Issued: 04/18/2006
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Kolinummi, Pasi, Vehviläinen, Juhani
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): TRAN, VINCENT HUY
• Application Number:
  US10/323,577
• Publication Number:
  US 20030131268A1
• Time in Patent Office: 1,216 Days
• Field of Search: 713/300, 713/320, 713/321, 713/323, 713/324
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and device is disclosed for implementing dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at least one or several hardware units (201, 202, 203), a hardware based power control logic (204) substantially implemented with logic circuits, as well as a programmable power control mode register (208) containing information about powered-down modes defined for said one or more hardware units. To transfer a single hardware unit (201, 202, 203) from the powered-down mode to the operational mode, the hardware unit transmits to the power control logic (204) a first level sensitive status signal (201a, 202a, 203a) for transferring the hardware unit from the powered-down mode to the wake up mode, and further a second level sensitive status signal (201b, 202b, 203b) for transferring the hardware unit from the wake up mode to the actual operating mode.

Claims

1. A method for dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at least one hardware unit, a hardware based power control logic implemented using logic circuits and a programmable power control mode register containing information about powered-down modes defined for said hardware units, in which method

a single hardware unit transmits, by means of a hardware-unit-specific level-sensitive status signal, information about its activity to the power control logic,

the power control mode register transmits, by means of a hardware-unit-specific level-sensitive requirement signal, information to the power control logic about the powered-down mode defined into said mode register by programming, wherein

the power control logic combines said status signal and said requirement signal and, on the basis of this, transfers said hardware unit from the powered-down mode to the operational mode by influencing the clock frequency, or the clock frequency together with the operating voltage to be supplied to said hardware unit by a clock frequency control unit and an operating voltage control unit,

wherein to transfer a single hardware unit from the powered-down mode to the operational mode, said hardware unit transmits to the power control logic

a first level-sensitive status signal for transferring said hardware unit from the powered-down mode to a wake up mode, and further

a second level-sensitive status signal for transferring said hardware unit from the wake up mode to the actual operational mode.

2. A power control system for dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at lease one hardware unit, a hardware based power control logic implemented using logic circuits, and a programmable power control mode register containing information about powered-down modes defined for said hardware unit, in which power control system

a single hardware unit is arranged to transmit, by means of a hardware-unit-specific level-sensitive status signal, information about its activity to the power control logic,

the power control mode register is arranged to transmit, by means of a hardware-unit-specific level-sensitive requirement signal, information to the power control logic about the powered-down mode defined into said mode register by programming for a single hardware unit, wherein

the power control logic is arranged to combine said status signal and said requirement signal for transferring said hardware unit from the powered-down mode to the operational mode by influencing the clock frequency, or the clock frequency together with the operating voltage to be supplied to said hardware unit by a clock frequency control unit and an operating voltage control unit,

wherein to transfer a single hardware unit from the powered-down mode, said hardware unit is arranged to transmit to the power control logic

a first level-sensitive status signal for transferring said hardware unit from the powered-down mode to a wake up mode, and further

a second level-sensitive status signal for transferring said hardware unit from the wake up mode to the actual operational mode.

3. The power control system according to claim 2, wherein the first and second hardware-unit-specific level-sensitive status signals as well as the hardware-unit-specific requirement signal are all binary digital signals, which signals have two different logical states, 0 and 1.

4. The power control system according to claim 3, wherein several parallel binary requirement signals are used to define several powered-down modes for one hardware unit.

5. The power control system according to claim 2 wherein the power control logic is arranged to individually meet the requirements of each hardware unit with respect to the clock frequency and/or operating voltage.

6. The power control system according to claim 2, wherein the power control logic is arranged to combine the first and second status signals ofseveral hardware units, and to supply all of said hardware units with the same clock frequency/frequencies and/or operating voltage/voltages according to the requirements of the most active hardware unit.

7. The power control system according to claim 2, wherein the single hardware unit comprises means for activating said first and second status signals at a moment of time which has been predetermined by software.

8. The power control system according to claim 7, wherein said means are arranged to operate at a reduced clock frequency and/or at a reduced operating voltage.

9. The power control system according to claim 2, wherein the power control system is arranged to be used in application specific integrated circuits (ASIC).

10. The power control system according to claim 2, wherein the power control system is arranged to be used in a mobile station.