Laser-induced critical parameter analysis of CMOS devices
First Claim
1. A system for critical parameter analysis (CPA) of a semiconductor device (DUT), comprising:
- a laser scanning microscope (LSM);
automated test apparatus (ATE) for providing predefined stimulus to the semiconductor device (DUT), for comparing responses from the semiconductor device (DUT) against a set of predefined expected responses, and for generating a short output pulse when a difference is detected between responses from said semiconductor device (DUT) and said predefined expected responses, said automated test apparatus being connected to the DUT while the DUT is disposed within a scanning chamber of said laser scanning microscope (LSM);
display means for displaying an image of said semiconductor device produced by said laser scanning microscope (LSM);
means for overlaying a visible representation of said short output pulse on said displayed image to indicate a corresponding position on the semiconductor device (DUT) of a scanning beam of the laser scanning microscope (LSM) at the time the output pulse was generated; and
means for simultaneously scanning said semiconductor device (DUT) with said laser scanning microscope (LSM) while said ATE repeatedly applies said predefined stimulus to said DUT and compares responses therefrom against said predefined expected responses;
whereinthe automated test apparatus (ATE) and the semiconductor device (DUT) form a closed loop feedback system;
the automated test apparatus (ATE) is programmed to ‘
break’
in or out of a vector loop which is detecting pass/fail operation of the semiconductor device (DUT); and
said automated test apparatus (ATE) is configured to repeatedly cycle (“
short-cycle”
) said predefined stimulus from a starting point up to a point of failure when such failure is detected.
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Abstract
A technique is described for performing critical parameter analysis (CPA) of a semiconductor device (DUT) by combining the capabilities of conventional automated test equipment (ATE) with a focused optical beam scanning device such as a laser scanning microscope (LSM). The DUT is provided with a fixture such that it can be simultaneously scanned by the LSM or a similar device and exercised by the ATE. The ATE is used to determine pass/fail boundaries of operation of the DUT. Repeatable pass/fail limits (for timing, levels, etc.) are determined utilizing standard test patterns and methodologies. The ATE vector pattern(s) can then be programmed to “loop” the test under a known passing or failing state. When light energy from the LSM scanning beam sufficiently disturbs the DUT to produce a transition (i.e., to push the device outside of its critical parameter limits), this transition is indicated on the displayed image of the DUT, indicating to the user which elements of the DUT were implicated in the transition.
31 Citations
20 Claims
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1. A system for critical parameter analysis (CPA) of a semiconductor device (DUT), comprising:
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a laser scanning microscope (LSM); automated test apparatus (ATE) for providing predefined stimulus to the semiconductor device (DUT), for comparing responses from the semiconductor device (DUT) against a set of predefined expected responses, and for generating a short output pulse when a difference is detected between responses from said semiconductor device (DUT) and said predefined expected responses, said automated test apparatus being connected to the DUT while the DUT is disposed within a scanning chamber of said laser scanning microscope (LSM); display means for displaying an image of said semiconductor device produced by said laser scanning microscope (LSM); means for overlaying a visible representation of said short output pulse on said displayed image to indicate a corresponding position on the semiconductor device (DUT) of a scanning beam of the laser scanning microscope (LSM) at the time the output pulse was generated; and means for simultaneously scanning said semiconductor device (DUT) with said laser scanning microscope (LSM) while said ATE repeatedly applies said predefined stimulus to said DUT and compares responses therefrom against said predefined expected responses; wherein the automated test apparatus (ATE) and the semiconductor device (DUT) form a closed loop feedback system; the automated test apparatus (ATE) is programmed to ‘
break’
in or out of a vector loop which is detecting pass/fail operation of the semiconductor device (DUT); andsaid automated test apparatus (ATE) is configured to repeatedly cycle (“
short-cycle”
) said predefined stimulus from a starting point up to a point of failure when such failure is detected. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for critical parameter analysis (CPA) of a semiconductor device (DUT), comprising:
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providing a focused optical beam scanning device; providing automated test apparatus (ATE) for providing predefined stimulus to the semiconductor device (DUT), for comparing responses from the semiconductor device (DUT) against a set of predefined expected responses, and for generating a short output pulse when a difference is detected between responses from said semiconductor device (DUT) and said predefined expected responses, said automated test apparatus being connected to the DUT while the DUT is disposed within a scanning chamber of said laser scanning microscope (LSM); displaying an image of said semiconductor device produced by said laser scanning microscope (LSM); overlaying a visible representation of said short output pulse on said displayed image to indicate a corresponding position on the semiconductor device (DUT) of a scanning beam of the laser scanning microscope (LSM) at the time the output pulse was generated; and simultaneously scanning said semiconductor device (DUT) with said laser scanning microscope (LSM) while repeatedly applying said redefined stimulus to said DUT and comparing responses therefrom against said predefined expected responses using said ATE; wherein the automated test apparatus (ATE) and the semiconductor device (DUT) form a closed loop feedback system; the automated test apparatus (ATE) is programmed to ‘
break’
in or out of a vector loop which is detecting pass/fail operation of the semiconductor device (DU); andsaid automated test apparatus (ATE) is configured to repeatedly cycle (“
short-cycle”
) said predefined stimulus from a starting point up to a point of failure when such failure is detected. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification