Integrated circuit with improved channel stress properties and a method for making it

• US 7,045,408 B2
• Filed: 05/21/2003
• Issued: 05/16/2006
• Est. Priority Date: 05/21/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Armstrong, Mark, Hoffmann, Thomas, Auth, Chris, Cea, Stephen
• Primary Examiner(s): LUU, CHUONG A
• Application Number:
  US10/443,152
• Publication Number:
  US 20040235236A1
• Time in Patent Office: 1,091 Days
• Field of Search: 438/199, 438/763, 438/744, 438/141, 438/158, 438/283, 438/380, 438/740
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.

Claims

1. A method for forming an integrated circuit comprising:

forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate;

forming a silicate glass buffer layer on only the PMOS transistor structure or the NMOS transistor structure; and

forming and retaining a highly stressed etch stop layer on the silicate glass buffer layer and on both the PMOS transistor structure and the NMOS transistor structure, wherein the silicate glass buffer layer reduces stress transfer from the etch stop layer to the PMOS or NMOS transistor structure upon which the buffer layer is formed.

2. The method of claim 1 wherein the etch stop layer is in tension and the silicate glass layer is formed on the PMOS transistor structure.

3. The method of claim 1 wherein the etch stop layer is in compression and the silicate glass layer is formed on the NMOS transistor structure.

4. The method of claim 1 wherein the silicate glass layer has a thickness of between about 100 and about 2,000 angstroms and comprises a silicon dioxide layer.

5. The method of claim 2 further comprising:

forming a gate electrode that has a top surface, a first side surface and a second side surface, the gate electrode positioned between a source region and a drain region;

forming first and second spacers along the first and second side surfaces and on the source and drain regions;

forming the etch stop layer on the first and second spacers, on the source and drain regions, and on the top surface of the gate electrode; and

removing the etch stop layer from the top surface of the gate electrode.

6. The method of claim 5 wherein the etch stop layer is removed from the top surface of the gate electrode using a chemical mechanical polishing process.

7. The method of claim 6 wherein the etch stop layer has a thickness of between about 100 and about 1,500 angstroms and comprises silicon nitride.

8. A method for forming an integrated circuit comprising:

forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, the NMOS transistor structure having a gate electrode that has a top surface, a first side surface and a second side surface;

forming a silicate glass buffer layer on only the PMOS transistor structure;

forming a highly stressed etch stop layer on the silicate glass buffer layer and along the first side surface and the second side surface of the gate electrode, and on the top surface of the gate electrode; and

removing the etch stop layer from the top surface of the gate electrode, while retaining the etch stop layer along the first side surface and along the second side surface of the gate electrode, and retaining the etch stop layer on the silicate glass buffer layer,

wherein the highly stressed etch stop layer transfers stress to the NMOS transistor structure, and

wherein the silicate glass buffer layer reduces stress transfer from the etch stop layer to the PMOS transistor structure.

9. The method of claim 8 wherein the etch stop layer is removed from the top surface of the gate electrodes using a chemical mechanical polishing process.

10. The method of claim 8 wherein the silicate glass layer has a thickness of between about 100 and about 2,000 angstroms and comprises silicon dioxide.

11. The method of claim 8 wherein the etch stop layer has a thickness of between about 100 and about 1,500 angstroms and comprises silicon nitride.

12. The method of claim 8 wherein the silicate glass layer is formed on only the PMOS transistor structure by forming the silicate glass layer on both the PMOS transistor structure and the NMOS transistor structure, masking the silicate glass layer where it covers the PMOS transistor structure, and removing the silicate glass layer where it covers the NMOS transistor structure.