Data processing structure

• US 7,047,342 B2
• Filed: 02/25/2002
• Issued: 05/16/2006
• Est. Priority Date: 05/31/2001
• Status: Expired due to Fees

• Current Assignee: Wittenstein AG
• Original Assignee: Wittenstein AG
• Inventors: Krug, Andreas, Kalker, Thomas
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): SPITTLE, MATTHEW D
• Application Number:
  US10/478,554
• Publication Number:
  US 20040139263A1
• Time in Patent Office: 1,541 Days
• Field of Search: 710/108
• US Class Current: 710/305
• CPC Class Codes: B25J 9/1602 characterised by the control system, structure, architecture
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G05B 19/4148 characterised by using several processors for different functions, distributed (real-time) systems G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33168 Two bus, master bus and local servo bus
• CPC Class Codes: G05B 2219/33281 Archictecture, nodes for communication and measuring on serial bus

Abstract

A data processing structure comprising a plurality of processors ad a data bus for a data communication with a serial data structure. The plurality of processors can be respectively coupled in parallel to the data bus, and a data communication via the data bus with one of the processors, preferably a programming of the processor, is authorized for the same, but is blocked for all of the other processors.

Claims

1. A data processing structure comprising a plurality of processors controlled by a field bus, a data bus for data communication with a serial data structure, the plurality of processors are connected in parallel to both the field bus and the data bus, wherein, for data communication with one of the plurality of processors via the data bus, the one processor is connected to the data bus, while all the others of the plurality of processors are disconnected from the data bus.

2. A data processing structure according to claim 1, wherein the plurality of processors are connected to the data bus in a parallel connection, and data communication via the data bus with the one of the plurality of processors for programming the one processor is permitted for and prohibited for all the others of the plurality of processors.

3. The data processing structure according to claim 2, wherein, for the data communication via the data bus the one processor is connected to the data bus, while all the others of the plurality of processors are disconnected from the data bus.

4. The data processing structure according to claim 1, wherein, in each case, one switching unit is connected between each processor and the data bus, wherein the switching unit is either connecting a processor to the data bus or disconnecting it from the data bus.

5. The data processing structure according to claim 4, wherein the plurality of processors are controlled via a field bus in a parallel connection.

6. The data processing structure according to claim 5, wherein each processor is assigned in each case one control unit, the control units are connected to the field bus, and the control units can receive control signals via the field bus in order either to connect the respective processors to the data bus via the associated switching units, or to disconnect them from the data bus.

7. A drive controller, preferably for a robot, having a data processing structure according to claim 1.