Wide dynamic range operation for CMOS sensor with freeze-frame shutter
First Claim
1. A method of obtaining an image signal using a CMOS sensor with a freeze-frame shutter comprising:
- collecting a short image signal during a first time period;
sampling the short image signal after the first time period;
collecting a long image signal during a second time period;
sampling the long image signal after the second time period; and
combining the short image signal and the long image signal in an analog memory in the sensor to create a total image signal.
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Abstract
Wide dynamic range operation is used to write a signal in a freeze-frame pixel into the memory twice, first after short integration and then after long integration. The wide dynamic range operation allows the intra-scene dynamic range of images to be extended by combining the image taken with a short exposure time with the image taken with a long exposure time. A freeze-frame pixel is based on voltage sharing between the photodetector PD and the analog memory. Thus, with wide dynamic range operation, the resulting voltage in the memory may be a linear superposition of the two signals representing a bright and a dark image after two operations of sampling.
37 Citations
17 Claims
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1. A method of obtaining an image signal using a CMOS sensor with a freeze-frame shutter comprising:
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collecting a short image signal during a first time period; sampling the short image signal after the first time period; collecting a long image signal during a second time period; sampling the long image signal after the second time period; and combining the short image signal and the long image signal in an analog memory in the sensor to create a total image signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A freeze-frame pixel using wide dynamic range operating comprising:
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a photodetector having a memory; an analog memory; and a plurality of switches including; a first switch constructed to connect the photodetector to a reset voltage source; a second switch constructed to connect the photodetector to the analog memory for permitting transfer of a first and a second image signal collected in the photodetector during a respective first and second collection time period; and a third switch for connecting the analog memory to a reset voltage source, wherein the third switch is different than either the first or the second switch, and wherein the analog memory is constructed such that it is able to combine the first image signal and the second image signal to create a total image signal. - View Dependent Claims (9, 10, 11)
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12. A method of operating a CMOS image sensor comprising:
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resetting an analog memory of the image sensor by activating a first switch and connecting the analog memory to a reset voltage source; resetting a photodetector of the image sensor by activating a second switch; integrating charge at the photodetector during a first integration period to generate a first image signal; transferring the first image signal from the photodetector to the memory by activating a third switch; integrating charge at the photodetector during a second integration period to generate a second image signal; transferring the second image signal from the photodetector to the memory by activating the third switch; and creating a total image signal in the analog memory by combining the first and the second image signals. - View Dependent Claims (13)
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14. An array of image sensor cells comprising:
a plurality of pixels arranged in an array and comprising; a photodetector having a memory; an analog memory; and a plurality of switches including; a first switch constructed to connect the photodetector to a reset voltage source; a second switch constructed to connect the photodetector to the analog memory for permitting transfer of a first and a second image signal collected in the photodetector during a respective first and second collection time period, wherein the analog memory is constructed such that it can create a total image signal based on the first and the second image signals; and a third switch for connecting the analog memory to a reset voltage source, wherein the third switch is different than either the first or the second switch. - View Dependent Claims (15, 16, 17)
Specification