System and method for detecting defects in a thin-film-transistor array

• US 7,053,645 B2
• Filed: 06/06/2003
• Issued: 05/30/2006
• Est. Priority Date: 06/06/2003
• Status: Expired due to Fees

• Current Assignee: Yieldboost Technologies Incorporated
• Original Assignee: Yieldboost Technologies Incorporated
• Inventors: Chung, Kyo Young
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/455,359
• Publication Number:
  US 20040246015A1
• Time in Patent Office: 1,089 Days
• Field of Search: 324/765, 324768-770, 324/71.3, 324/158.1, 349/187, 349/192, 438/14, 438 17- 18
• US Class Current: 324/760.02
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: H04N 17/04 for receivers

Abstract

A system and method for detecting a defect in a transistor array includes applying a test signal to the array, monitoring pixel voltages along a gate line of the array, and detecting a defect associated with the gate line based on a variation in the pixel voltages along the gate line during the monitoring step. The system and method can also detect a precise location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

Claims

1. A method for detecting a defect in a transistor array including one or more gate lines arranged at least substantially parallel to one or more respective common lines, said method comprising:

applying a test signal to the array;

monitoring pixel voltages at different monitoring points along a gate line of the array; and

detecting a short defect between the gate line and a common line at a location where the gate line and the common line are arranged parallel to one another, the short defect being detected based on how the pixel voltages vary from one monitoring point to another monitoring point during said monitoring step.

2. The method of claim 1, wherein a common line and the gate line associated with the defect are connected to a same transistor element in the array.

3. The method of claim 1, wherein a common line and the gate line associated with the defect are connected to different transistor elements in the array.

4. The method of claim 1 further comprising:

detecting a location of the defect based on a change in slope of a profile of the pixel voltages.

5. The method of claim 1, further comprising:

detecting a location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

6. The method of claim 5, wherein the location of the defect corresponds to a point along the gate line where the variation changes from increasing pixel voltages to decreasing pixel voltages.

7. The method of claim 5, wherein the location of the defect corresponds to a point along the gate line where the variation changes from decreasing pixel voltages to increasing pixel voltages.

8. The method of claim 1, further comprising:

detecting a location of the defect based on one of a minimum value or a maximum value on a pixel voltage profile.

9. The method of claim 1, wherein the transistor array is a TFT array.

10. The method of claim 1, wherein the pixel voltage profile includes a time axis that is in one-to-one correspondence with respective locations along the gate line, and wherein the location of the short defect is determined to correspond to a point on the time axis where a rate of change in variation of the pixel voltage profile exceeds a predetermined level.

11. The method of claim 10, wherein the rate of change in variation of the pixel voltage profile exceeds said predetermined level when the pixel voltage profile transitions from a positive to a negative value or from a negative to a positive value.

12. The method of claim 10, wherein the rate of change in variation of the pixel voltage profile exceeds said predetermined level when the pixel voltage profile transitions from a minimum to a maximum value or from a maximum to a minimum value.

13. The method of claim 10, wherein the short defect is associated with a specific pixel in a display.

14. A system for detecting a defect in a transistor array including one or more gate lines arranged at least substantially parallel to one or more respective common lines, said system comprising:

a signal generator which applies a test signal pattern to the array; and

a detector which detects a short defect in the array between the gate line and a common line at a location where the gate line and the common line are arranged parallel to one another, the short defect being detected based on how pixel voltages vary between monitoring points along an array gate line.

15. The system of claim 14, wherein a common line and the gate line associated with the defect are connected to a same transistor element in the array.

16. The system of claim 14, wherein a common line and the gate line associated with the defect are connected to different transistor elements in the array.

17. The system of claim 14, wherein the detector detects a location of the defect based on a change in slope of a profile of the pixel voltages.

18. The system of claim 14, wherein the detector detects a location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

19. The system of claim 18, wherein the location of the defect corresponds to a point along the gate line where the variation changes from increasing pixel voltages to decreasing pixel voltages.

20. The system of claim 18, wherein the location of the defect corresponds to a point along the gate line where the variation changes from decreasing pixel voltages to increasing pixel voltages.

21. The system of claim 14, wherein the transistor array is a TFT array.

22. A signal analyzer for testing a TFT array including one or more gate lines arranged at least substantially parallel to one or more respective common lines, said analyzer comprising:

at least one electrode for inputting a test signal into the TFT array; and

a processor which monitors how pixel voltages vary between monitoring points along a gate line of the array, and detects a short defect associated with the gate line based on the variation, wherein the short defect is between the gate line and a common line at a location where the gate line and the common line are arranged parallel to one another.

23. The signal analyzer of claim 22, wherein the common line and the gate line are connected to a same transistor element in the array.

24. The signal analyzer of claim 22, wherein the common line and the gate line are connected to different transistor elements in the array.

25. The signal analyzer of claim 22, wherein the processor detects a location of the defect based on a change in slope of a profile of the pixel voltages.

26. The signal analyzer of claim 22, wherein the processor detects a location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

27. The signal analyzer of claim 26, wherein the location of the defect corresponds to point along the gate line where the variation changes from increasing pixel voltages to decreasing pixel voltages.

28. The signal analyzer of claim 26, wherein the location of the defect corresponds to point along the gate line where the variation changes from decreasing pixel voltages to increasing pixel voltages.

29. The signal analyzer of claim 22, wherein the transistor array is a TFT array.