Semiconductor device, method for manufacturing the same, and plating solution

• US 7,060,618 B2
• Filed: 08/13/2002
• Issued: 06/13/2006
• Est. Priority Date: 08/13/2001
• Status: Active Grant

• Current Assignee: Ebara Corporation
• Original Assignee: Ebara Corporation
• Inventors: Kimura, Norio, Inoue, Hiroaki, Wang, Xinming, Kanayama, Makoto, Matsumoto, Moriji
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US10/216,902
• Publication Number:
  US 20030075808A1
• Time in Patent Office: 1,400 Days
• Field of Search: 438/660, 438/633, 438/626, 438/627, 438637-640, 438/643, 438/687, 438/692, 438/678, 438/685
• US Class Current: 438/687
• CPC Class Codes: C23C 18/1608 from pretreatment step, i.e. selective pre-treatment
• CPC Class Codes: C23C 18/1632 Features specific for the apparatus, e.g. layout of cells and of its equipment, multiple cells
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/32 Coating with nickel, cobalt or mixtures thereof with phosphorus or boron C23C18/50 takes precedence
• CPC Class Codes: C23C 18/48 Coating with alloys
• CPC Class Codes: C23C 18/50 with alloys based on iron, cobalt or nickel
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surface of a semiconductor substrate, and also has a protective film formed on surfaces of exposed interconnects that define the interconnect structure, to protect the interconnects. The protective film has a flattened surface.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing an insulating film having recesses therein which are partially filled by a seed layer that covers a surface of said insulating film;

plating an electrically conductive material onto said seed layer so as to embed said electrically conductive material in said recesses;

removing said electrically conductive material and said seed layer from said surface of said insulating film, whereby interconnects of said electrically conductive material are formed in said insulating film;

cleaning said surface of said insulating film with a cleaning liquid containing an alkaline surfactant to reduce an electrical conductor contamination on said insulating film;

electroless plating a material onto exposed surfaces of said interconnects, thereby selectively forming a protective film on said exposed surfaces; and

flattening a surface of said protective film to eliminate unevenness of a thickness of said protective film and to remove an overhanging portion of said protective film.

2. The method according to claim 1, wherein

cleaning said surface of said insulating film comprises cleaning said surface of said insulating film such that an electrical conductor contamination on said insulating film is reduced to at most 5×

10⁵ atoms/cm².

3. The method according to claim 1, further comprising:

performing a pre-plating treatment prior to electroless plating said material onto said exposed surfaces.

4. The method according to claim 1, wherein

flattening said surface of said protective film comprises flattening said surface until said surface is at the same level as that of said surface of said insulating film.

5. A method for manufacturing a semiconductor device, comprising:

providing an insulating film having recesses therein which are partially filled with a first seed layer that covers a surface of said insulating film;

plating an electrically conductive material onto said first seed layer so as to embed said electrically conductive material in said recesses;

removing said electrically conductive material and said first seed layer from said surface of said insulating film, whereby interconnects of said electrically conductive material are formed in said insulating film;

electroless plating an amorphous Co—

B alloy onto exposed surfaces of said interconnects, thereby selectively forming on said exposed surfaces a second seed layer of an amorphous Co—

B alloy; and

directly electroless plating a material onto a surface of said second seed layer, thereby forming a protective film on said surface of said second seed layer,

with said amorphous Co—

B alloy acting as a catalyst during the electroless plating of said material onto said surface of said second seed layer.

6. The method according to claim 5, wherein

directly electroless plating said material onto said surface of said second seed layer comprises directly electroless plating one of a Co—

W—

B alloy and a Co—

W—

P alloy onto said surface.