Address buffer circuit for memory device
DC
First Claim
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1. An address buffer circuit for a memory device, the address buffer circuit comprising:
- a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and
a control unit for controlling operation of the second address input buffer group, wherein,operation of the first address input buffer group is controlled by a first control signal, and the control unit receives a second control signal enabled when all banks of the memory device enter an active state and controls operation of the second address input buffer group.
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Abstract
Disclosed is an address buffer circuit for a memory device, the address buffer circuit comprising: a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and a control unit for controlling operation of the second address input buffer group. Herein, operation of the first address input buffer group is controlled by a first control signal, and the control unit receives a second control signal enabled when all banks of the memory device enter an active state and controls operation of the second address input buffer group.
13 Citations
4 Claims
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1. An address buffer circuit for a memory device, the address buffer circuit comprising:
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a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and a control unit for controlling operation of the second address input buffer group, wherein, operation of the first address input buffer group is controlled by a first control signal, and the control unit receives a second control signal enabled when all banks of the memory device enter an active state and controls operation of the second address input buffer group. - View Dependent Claims (2, 3, 4)
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Specification
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Litigation Data
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Current AssigneeHynix Semiconductor Incorporated (SK Hynix Inc.)
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Original AssigneeHynix Semiconductor Incorporated (SK Hynix Inc.)
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InventorsChun, Jun Hyun
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Primary Examiner(s)Ho, Hoai V.
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Application NumberUS11/108,308Publication NumberTime in Patent Office421 DaysField of Search365/193, 365/203, 365/230.03, 365/230.08US Class Current365/230.08CPC Class CodesG11C 11/4082 Address Buffers; level conv...G11C 7/1066 Output synchronizationG11C 8/06 Address interface arrangeme...
