Address buffer circuit for memory device

  • US 7,061,824 B2
  • Filed: 04/18/2005
  • Issued: 06/13/2006
  • Est. Priority Date: 09/13/2004
  • Status: Active Grant
First Claim
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1. An address buffer circuit for a memory device, the address buffer circuit comprising:

  • a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and

    a control unit for controlling operation of the second address input buffer group, wherein,operation of the first address input buffer group is controlled by a first control signal, and the control unit receives a second control signal enabled when all banks of the memory device enter an active state and controls operation of the second address input buffer group.

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