Task based adaptative profiling and debugging

• US 7,062,304 B2
• Filed: 08/17/2001
• Issued: 06/13/2006
• Est. Priority Date: 08/21/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard, D'Inverno, Dominique
• Primary Examiner(s): Tsang, Fan
• Assistant Examiner(s): Hashem, Lisa
• Application Number:
  US09/932,136
• Publication Number:
  US 20020053684A1
• Time in Patent Office: 1,761 Days
• Field of Search: 700/79, 713/324
• US Class Current: 455/574
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 11/3013 where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems testing or monitoring of control systems or parts thereof G05B23/02
• CPC Class Codes: G06F 11/3017 where the computing system is implementing multitasking multiprogramming arrangements G06F9/46; allocation of resources G06F9/50
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation. Further, activity counters may be selectively enabled for specific tasks in order to obtain more accurate profile information.

Claims

1. A method of generating energy profiles for a specific task in a processing device executing multiple tasks, comprising the steps of:

receiving a first task identifier indicative of an active task in a processing component;

receiving hardware activity signals each indicative of a hardware event in the processing device;

storing a second task identifier indicating a task to be monitored;

comparing the first and second task identifiers and generating a predetermined signal if the first and second task identifiers match;

measuring activity corresponding to the task to be monitored by counting hardware activity signals received during generation of said predetermined signal.

2. The method of claim 1 further comprising:

periodically updating with a period T an energy profile responsive to said measuring step during operation of said processing device.

3. The method of claim 2 and further comprising the step of executing a plurality of tasks in accordance with a scenario defining scheduling of said plurality of tasks and modifying said scenario responsive to said step of updating an energy profile.

4. The method of claim 1 and further comprising the step of performing a debugging operation responsive to said measuring step.

5. The method of claim 1 wherein:

said hardware event in the processing device includes a cache miss.

6. The method of claim 1 wherein:

said hardware event in the processing device includes a translation lookaside buffer miss.

7. The method of claim 1 wherein:

said hardware event in the processing device includes a non-cacheable memory access.

8. The method of claim 1 wherein:

said hardware event in the processing device includes a wait time.

9. The method of claim 1 wherein:

said hardware event in the processing device includes a read/write requests for a predetermined resource.

10. The method of claim 2 wherein:

said period T corresponds to a thermal time constant of the processing device.

11. A processing device for multitasking multiple tasks comprising:

circuitry for receiving a first task identifier selected from among a plurality of possible task identifiers indicative of an active task in a processing component;

circuitry for receiving hardware activity signals each indicative of a hardware event in the processing device;

a memory for storing a plurality of second task identifier, each second task identifier corresponding to a task to be monitored;

a comparator for comparing the first and second task identifiers and generating a predetermined second task identifier match signal if the first task identifier matches a corresponding one of said second task identifiers;

a plurality of counters, each counter corresponding to one of said stored plurality of second task identifiers, each counter enabled to count said hardware activity signals when said comparator generates a corresponding predetermined second task identifier match signal.

12. The processing device of claim 11 wherein:

said processing device is operable to periodically update with a period T an energy profile from counts of said plurality of counters during operation of said processing device.

13. The processing device of claim 12 wherein said plurality of tasks are executed in accordance with a scenario defining scheduling of said plurality of tasks and said scenario is updated responsive to said step of updating an energy profile.

14. The processing device of claim 11 and further comprising circuitry for implementing a debugging operation responsive to values in said plurality of counters.

15. The processing device of claim 11 wherein:

said hardware event in the processing device includes a cache miss.

16. The processing device of claim 11 wherein:

said hardware event in the processing device includes a translation lookaside buffer miss.

17. The processing device of claim 11 wherein:

said hardware event in the processing device includes a non-cacheable memory access.

18. The processing device of claim 11 wherein:

said hardware event in the processing device includes a wait time.

19. The processing device of claim 11 wherein:

said hardware event in the processing device includes a read/write requests for a predetermined resource.

20. The processing device of claim 12 wherein:

said period T corresponds to a thermal time constant of the processing device.