CMOS image sensor with a low-power architecture

• US 7,068,319 B2
• Filed: 02/01/2002
• Issued: 06/27/2006
• Est. Priority Date: 02/01/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Barna, Sandor L., Cho, Kwang-Bo, Panicacci, Roger, Rossi, Guiseppe
• Primary Examiner(s): Ometz, David
• Assistant Examiner(s): Villecco, John M.
• Application Number:
  US09/683,679
• Publication Number:
  US 20030146991A1
• Time in Patent Office: 1,607 Days
• Field of Search: 348/302, 348/372, 348/294, 348/211.4, 348/222.1, 348/229.1, 348/230.1, 348/273, 348/280, 348/281, 348/300, 348/313, 348/312, 348/316, 348/319, 250/208.1, 341/144, 341/155
• US Class Current: 348/372
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.

Claims

1. An image sensor, comprising:

an array of photosensing devices arranged into columns and rows;

a column readout part which reads out charges captured by said photosensing devices a row at a time;

a gain stage, coupled to receive an output of said column readout part, and to increase a signal level of said readout part output; and

an output driving stage, which drives an output signal,

wherein each of said column readout part, said gain stage, and said output driving stage include at least one element which optimizes a power consumption of the stage independent of other stages.

2. An image sensor as in claim 1, wherein said column readout part operates in a charge mode.

3. An image sensor as in claim 1, wherein said column readout part optimizes bias voltages.

4. An image sensor as in claim 3, wherein said column readout part produces specified bias voltages only during a time when those bias voltages are actually being used.

5. An image sensor as in claim 1, wherein said column readout part includes an element that minimizes a stray capacitance.

6. An image sensor as in claim 5, wherein said element that minimizes stray capacitance includes a multiplexer formed in multiple stages, each stage having fewer than all of the full number of signals.

7. An image sensor as in claim 1, wherein said gain stage includes isolation stages which isolate an actual element carrying out the gain from input and output.

8. An image sensor as in claim 1, wherein said gain stage includes an input unity gain buffer stage, an output unity gain buffer stage, and a gain stage coupled between said input unity gain buffers stage and said output unity gain buffer stage.

9. An image sensor as in claim 8, wherein each of said unity gain input stage, unity gain output stage and gain stage include at least one reset element which allows resetting of voltage there across.

10. An image sensor as in claim 8, further comprising an offset clock which operates said buffer stages at different times.

11. An image sensor as in claim 10, wherein said offset clock includes a two phase non overlapping clock in which the different buffer stages are clocked by different phases.

12. An image sensor as in claim 1, wherein said output driving stage includes an A/D converter.

13. An image sensor as in claim 12, wherein said A/D converter includes first and second A/D converters operating out of phase with one another.

14. An image sensor, as in claim 13, wherein one of said A/D converters is associated with first color pixels, and a second of said A/D converters is associated with second color pixels.

15. An image sensor as in claim 1, wherein said column readout part includes a timing and control logic which has multiple outputs, each of which can be independently turned off when not in use.

16. An image sensor, comprising:

an array of photosensitive pixels producing output signals indicative of values of said pixels; and

first and second A/D converters, said first A/D converter associated with first color pixels, and said second A/D converter associated with second color pixels, said first and second A/D converters having staggered operating timing, such that one of the A/D converters starts operating when a different A/D converter is continuing to operate, wherein said first A/D converter receives data from green pixels, and said second A/D converter receives data from red and blue pixels and

wherein said A/D converters are successive approximation A/D converters.

17. An image sensor, comprising:

an array of photosensitive pixels; and

timing and control logic, having a plurality of control parts, said plurality of control parts individually controllable and turned off when not in use,

wherein said control part includes a controllable bias element which is turned off to remove said bias when not in use, and wherein one of said plurality of control parts is a voltage clamp which is turned off when not in use.

18. An image sensor as in claim 17, wherein said controllable bias element includes a digitally controllable bias element.

19. An image sensor, comprising:

an array of photosensitive pixels;

timing and control logic, having a plurality of control parts, said plurality of control parts individually controllable and turned off when not in use; and

an element that minimizes parasitic capacitance on the readout bus, wherein said element includes an optimized gain element with first and second unity buffer stages, and a gain stage, said first and second buffer stages isolating a gain stage from the readout bus.

20. An image sensor, comprising:

an array of photosensitive pixels; and

timing and control logic, having a plurality of control parts, said plurality of control parts individually controllable and turned off when not in use,

wherein said timing and control logic produces a converter reference voltage, a clamped voltage, and a common mode feedback voltage, and

where each of said converter reference voltage, clamped voltage, and common mode feedback voltage are produced by separate, controllable sources, which are turned off when not in use.

21. A method, comprising:

reading out pixel values from an array of photosensitive pixels;

A/D converting pixel values from green pixels in a first A/D converter, at a first timing and

A/D converting pixel values from blue pixels in a second A/D converter at a second timing offset from said first;

timing,

wherein said second timing is 50 percent of the way through a conversion cycle represented by said first timing.

22. A method, comprising:

reading out pixel values from an array of photosensitive pixels;

A/D converting pixel values from green pixels in a first A/D converter, at a first timing; and

A/D converting pixel values from blue pixels in a second A/D converter at a second timing offset from said first timing,

wherein said A/D converting comprises successive approximation A/D converting.

23. A method of acquiring an image, comprising:

producing bias electrical values to be used as part of acquiring image signals; and

turning off said bias electrical signals at times during the acquiring when the biases are not needed, wherein the bias signals include a clamped signal.

24. A method as in claim 23, wherein said producing comprises mirroring a single bias value multiple times, and turning off said mirroring as said turning off.