Hardware debugging in a hardware description language

• US 7,069,526 B2
• Filed: 12/29/2004
• Issued: 06/27/2006
• Est. Priority Date: 11/30/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synplicity, Inc. (Synopsys Incorporated)
• Inventors: Beardslee, John Mark, Schubert, Nils Endric, Perry, Douglas L.
• Primary Examiner(s): Whitmore, Stacy A.
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US11/027,052
• Publication Number:
  US 20050125754A1
• Time in Patent Office: 545 Days
• Field of Search: 716 4- 8, 703 14- 16, 714/724
• US Class Current: 716/102
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Claims

1. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging a fabricated integrated circuit containing an electronic circuit design, the method comprising:

receiving a high level HDL description of the electronic circuit design;

determining aspects of the electronic circuit design to be examined or modified during debugging;

determining additional circuitry to be incorporated into the electronic circuit design to facilitate debugging;

producing a modified high level HDL description of the electronic circuit design by incorporating an HDL description of the additional circuitry into the high level HDL description of the electronic circuit design;

storing information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the modified high level HDL description; and

debugging the fabricated integrated circuit fabricated in accordance with the modified high level HDL description by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the modified high level HDL description or the high level HDL description.

2. The machine-readable medium as recited in claim 1, wherein at least a portion of the high level HDL description is written in a language selected from the group consisting of VHDL, Verilog HDL, C, C++ and SystemC.

3. The machine-readable medium as recited in claim 1, wherein debugging the fabricated integrated circuit does not require a testbench, wherein while debugging the fabricated integrated circuit, the fabricated integrated circuit is operating in its target environment without interruption and running at its target speed, and wherein the target environment includes real-time characteristics.

4. The machine-readable medium as recited in claim 1, wherein the method further comprises:

relating the debug information back to the high level HDL description for the electronic circuit design;

enabling a user to determine the aspects of the electronic circuit design to be examined or modified during debugging through interactive selection;

customizing the additional circuitry for use with at least a portion of the electronic circuit design; and

altering the additional circuitry to trade-off debugging coverage versus area cost.

5. The machine-readable medium as recited in claim 1, wherein the information about the additional circuitry further includes one or more trigger conditions and at least one of design control information, design visibility information and design patch information.

6. The machine-readable medium as recited in claim 1, wherein the fabricated integrated circuit is part of an electronic system that also includes software, wherein the method further comprises debugging the software, wherein the fabricated integrated circuit includes a processor, wherein the software is executed by the processor, and wherein debugging the fabricated integrated circuit is synchronized with debugging the software.

7. The machine-readable medium as recited in claim 6, wherein the hardware debugging system does not require a testbench, wherein while debugging the fabricated integrated circuit, the fabricated integrated circuit is operating in its target environment and running at its target speed, and wherein the target environment includes real-time characteristics.

8. The machine-readable medium as recited in claim 1, wherein the HDL description contains a hierarchical structure of HDL building blocks, wherein the electronic circuit design includes both analog and digital aspects, and wherein the aspects of the electronic circuit design to be examined or modified during debugging are determined in different ones of the HDL building blocks of the hierarchical structure.

9. The machine-readable medium as recited in claim 1, wherein the electronic circuit design includes at least one pre-designed block of circuitry having instrumentation circuitry, wherein the high level HDL description of the electronic circuit design is partitioned into two or more design parts, wherein the additional circuitry is partitioned into two or more partitions, each partition to debug a different part of the electronic circuit design, and wherein each design part contains its own additional circuitry to debug its corresponding design part.

10. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging an electronic system designed according to an electronic circuit design, the electronic circuit design being described by a high level HDL description, the method comprising:

receiving the high level HDL description of the electronic circuit design or a description derived therefrom;

determining aspects of the electronic circuit design to be examined or modified during debugging;

determining additional circuitry to be incorporated into the electronic circuit design to facilitate debugging;

incorporating the additional circuitry into the electronic circuit design;

storing information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the high level HDL description; and

debugging the electronic system by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the high level HDL description.

11. The machine-readable medium as recited in claim 10, wherein at least a portion of the high level HDL description is written in a language selected from the group consisting of VHDL, Verilog HDL, C, C++ and SystemC.

12. The machine-readable medium as recited in claim 10, wherein the method further comprises:

identifying functional failures that result from one or more of design errors, tool errors and manufacturing faults; and

identifying functional failures that result from specification errors.

13. The machine-readable medium as recited in claim 10, wherein debugging the electronic system does not require a testbench, wherein while debugging the electronic system, the electronic system is operating in its target environment and running at its target speed, and wherein the target environment includes real-time characteristics.

14. The machine-readable medium as recited in claim 10, wherein the high level HDL description contains a hierarchical structure of HDL building blocks, wherein the electronic circuit design includes both analog and digital aspects, and wherein the method further comprises determining, in different ones of the HDL building blocks of the hierarchical structure, aspects of the electronic circuit design to be examined or modified during debugging.

15. The machine-readable medium as recited in claim 10, wherein the method further comprises:

customizing the additional circuitry for use with at least a portion of the electronic circuit design;

altering the additional circuitry to trade-off debugging coverage versus area cost; and

implementing at least one of a design layout tool, a synthesis tool and a simulation tool.

16. The machine-readable medium as recited in claim 10, wherein the electronic system includes hardware and software, wherein the method further comprises debugging the hardware and the software together, wherein the electronic system includes a processor, the processor to execute the software, and wherein debugging the electronic circuit is synchronized with debugging the software.

17. The machine-readable medium as recited in claim 10, wherein the electronic system comprises at least one of an integrated circuit hardware product, a programmable integrated circuit and a printed circuit board with electronic components thereon, each of the integrated circuit hardware product, the programmable integrated circuit and the printed circuit board with electronic components thereon including at least a portion of the electronic circuit design.

18. The machine-readable medium as recited in claim 10, wherein the electronic circuit design includes at least one pre-designed block of circuitry having internal circuitry, wherein the electronic circuit design is partitioned into different sections, each different section of the electronic circuit design containing its own portion of the additional circuitry for debugging its corresponding section of the electronic circuit design, and wherein the additional circuitry is partitioned into different sections, each different section of the additional circuitry to debug a different portion of the electronic circuit design.

19. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging an electronic system having instrumentation circuitry included therein, wherein the electronic system is described with a hardware description language (HDL), the method comprising:

activating at least one aspect of the instrumentation circuitry available for debugging the electronic system via the instrumentation circuitry, the aspect selected from the group consisting of design visibility, design patching and design control;

determining configuration information based on the certain design visibility, design patching or design control aspects that are activated;

configuring the instrumentation circuitry in accordance with the configuration information;

receiving debug data from the configured instrumentation circuitry operating within the electronic system;

translating the debug data into HDL-related debug information; and

relating the HDL-related debug information to the HDL description of the electronic system.

20. The machine-readable medium as recited in claim 19, wherein at least a portion of the HDL description of the electronic system is written in a language selected from the group consisting of VHDL, Verilog HDL, C, C++ and SystemC.

21. The machine-readable medium as recited in claim 19, wherein the HDL description is a high-level HDL description and the HDL-related debug information is described in a high-level HDL, and wherein the method further comprises displaying the HDL description with the HDL-related debug information related thereto.

22. The machine-readable medium as recited in claim 19, wherein the method operates without any requirement for a testbench, wherein translating is performed automatically, and wherein the debug data includes at least status information or sampling data.

23. The machine-readable medium as recited in claim 19, wherein activating operates to enable a user to activate the certain design visibility, design patching or design control aspects, and wherein activating is performed using a graphical user interface.

24. The machine-readable medium as recited in claim 19, wherein the design control aspects include trigger conditions, and wherein activating operates to enable a user to set one or more trigger conditions from the trigger conditions available by the instrumentation circuitry.

25. The machine-readable medium as recited in claim 19, wherein the electronic system includes a hardware portion and a software portion, and wherein the method further comprises:

interacting with a software debugger that debugs the software of the electronic system; and

interacting with a functional simulator that simulates a portion of the electronic system.

26. The machine-readable medium as recited in claim 19, wherein the electronic system is operated in its target environment without interruption and running at its target speed during the debugging, and wherein the target environment includes real-time characteristics.

27. The machine-readable medium as recited in claim 19, wherein the method further comprises identifying at least one fault of the electronic system, wherein the at least one fault is selected from the group consisting of specification error, design error, tool error, device driver error, timing error, manufacturing fault and environment error.

28. The machine-readable medium as recited in claim 19, wherein the instrumentation circuitry comprises design instrumentation circuitry, wherein the method further comprises interoperating the design instrumentation circuitry with a logic analyzer, and wherein at least a portion of the debug data stems from the logic analyzer.

29. The machine-readable medium as recited in claim 19, wherein the electronic system comprises an integrated circuit product, and wherein the method further comprises:

examining the integrated circuit product by the instrumentation circuitry; and

modifying the behavior of the integrated circuit product by the instrumentation circuitry.

30. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging an integrated circuit product having instrumentation circuitry included therein, wherein the integrated circuit product was designed with a high-level HDL description of the integrated circuit product, the method comprising:

activating certain aspects available for examining or modifying by the instrumentation circuitry;

determining configuration information based on the certain aspects that are activated;

configuring the instrumentation circuitry in accordance with the configuration information;

receiving debug data from the configured instrumentation circuitry operating within the integrated circuit product;

translating the debug data into HDL-related debug information;

relating the HDL-related debug information to the high-level HDL description;

retrieving circuit status information for the integrated circuit product via the instrumentation circuitry; and

displaying state information concerning the integrated circuit product based on the retrieved circuit status information.

31. The machine-readable medium as recited in claim 30, wherein at least a portion of the HDL description of the electronic system being written in a language selected from the group consisting of HDL, Verilog HDL, C, C++ and SystemC.

32. The machine-readable medium as recited in claim 30, wherein the HDL-related debug information is described in a high-level HDL.

33. The machine-readable medium as recited in claim 30, wherein displaying comprises:

relating the state information to the high-level HDL description; and

displaying the high-level HDL description of the integrated circuit product with the state information related thereto, wherein the state information includes signal values for signals, and wherein relating operates to relate the signal values to HDL identifiers within the high-level HDL description that correspond to the signals.