Narrow width effect improvement with photoresist plug process and STI corner ion implantation

• US 7,071,515 B2
• Filed: 07/14/2003
• Issued: 07/04/2006
• Est. Priority Date: 07/14/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Shi-Shung, Wu, Chung-Cheng, Lin, Da-Wen, Sheu, Yi-Ming, Yeh, Po-Ying, Chen, Cheng-Ku
• Primary Examiner(s): Brewster, William M.
• Application Number:
  US10/619,114
• Publication Number:
  US 20050012173A1
• Time in Patent Office: 1,086 Days
• Field of Search: 257/506, 257/510, 257/519, 257/E21.546, 257/374, 438/435
• US Class Current: 257/374
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Claims

1. A NMOS transistor having an improved narrow width Vt roll-off, comprising:

a substrate that includes shallow trench isolation (STI) features which are comprised of a shallow trench with sloped sidewalls and a bottom, an oxide liner formed on said shallow trench sidewalls and bottom, and an insulator layer formed on said oxide liner that fills said shallow trench and extends to a level that is above the top of said substrate, wherein a groove is formed at top corners of said shallow trench;

an active area formed between two adjacent shallow trenches in said substrate, said active area having an indium doped region that is adjacent to the groove;

a gate dielectric layer formed on said active areas; and

a patterned gate layer formed on said gate dielectric layer wherein said gate layer extends over said adjacent shallow trenches.

2. The NMOS transistor of claim 1 wherein said substrate is also comprised of a second p-type dopant in said active areas.

3. The NMOS transistor of claim 1 wherein the depth of said shallow trench is about 1500 to 5000 Angstroms and the width of the shallow trench ranges from less than 100 nm to several microns.

4. The NMOS transistor of claim 1 wherein said oxide liner has a thickness of about 50 to 300 Angstroms.

5. The NMOS transistor of claim 1 wherein said insulator layer is comprised of SiO₂ or a low k dielectric material.

6. The NMOS transistor of claim 1 wherein said indium doped region has an indium concentration from about 10¹⁴ to 10¹⁹ ions/cm³ and has a thickness in the range of about 30 to 1000 Angstroms.

7. The NMOS transistor of claim 1 wherein said indium doped region extends away from said shallow trench to a distance between 0 and about 1000 Angstroms.

8. The NMOS transistor of claim 1 wherein said gate dielectric layer is comprised of SiO₂ or an upper high k dielectric metal oxide layer on a lower interfacial layer.

9. The NMOS transistor of claim 1 wherein said gate layer has a thickness of about 300 to 5000 Angstroms and forms a conformal layer on said gate dielectric layer and on said adjacent STI features.

10. The NMOS transistor of claim 1 wherein said gate layer is comprised of doped polysilicon.

11. The NMOS transistor of claim 1 wherein said gate layer is comprised of undoped polysilicon or amorphous silicon.

12. A NMOS transistor having an improved narrow width Vt roll-off, comprising:

a substrate that includes shallow trench isolation (STI) features which are comprised of a shallow trench with sloped sidewalls and a bottom, an oxide liner formed on said shallow trench sidewalls and bottom, and an insulator layer formed on said oxide liner that fills said shallow trench and extends to a level that is above the top of said substrate;

an active area formed between two adjacent shallow trenches in said substrate;

a gate dielectric layer formed on said active areas; and

a patterned gate layer formed on said gate dielectric layer wherein said gate layer extends over said adjacent shallow trenches;

wherein said active area having an indium doped region that is adjacent to top corners of said shallow trenches and extends under part of the gate dielectric layer.

13. The NMOS transistor of claim 12 wherein said substrate is also comprised of a second p-type dopant in said active areas.

14. The NMOS transistor of claim 12 wherein the depth of said shallow trench is about 1500 to 5000 Angstroms and the width of the shallow trench ranges from less than 100 nm to several microns.

15. The NMOS transistor of claim 12 wherein said oxide liner has a thickness of about 50 to 300 Angstroms.

16. The NMOS transistor of claim 12 wherein said insulator layer is comprised of SiO₂ or a low k dielectric material.

17. The NMOS transistor of claim 12 wherein said indium doped region has an indium concentration from about 10¹⁴ to 10¹⁹ ions/cm³ and has a thickness in the range of about 30 to 1000 Angstroms.

18. The NMOS transistor of claim 12 wherein said indium doped region extends away from said shallow trench to a distance between 0 and about 1000 Angstroms.

19. The NMOS transistor of claim 12 wherein said gate dielectric layer is comprised of SiO₂ or an upper high k dielectric metal oxide layer on a lower interfacial layer.

20. The NMOS transistor of claim 12 wherein said gate layer has a thickness of about 300 to 5000 Angstroms and forms a conformal layer on said gate dielectric layer and on said adjacent STI features.