Architecture for generating adaptive arbitrary waveforms

• US 7,072,781 B1
• Filed: 07/06/2004
• Issued: 07/04/2006
• Est. Priority Date: 07/06/2004
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bill, Colin S., Fang, Tzu-Ning, Gershon, Eugen, Gaun, David
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): SUGLO, JANET L
• Application Number:
  US10/885,284
• Time in Patent Office: 728 Days
• Field of Search: 702/58, 702/63, 702/66, 702/117, 324/426, 324/436, 324/603
• US Class Current: 702/63
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation

Abstract

A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.

Claims

1. A system that facilitates testing a device, comprising:

a signal component that generates an output signal for application to the device;

a monitor component that monitors one or more parameters of the device while the device is being tested, and communicates with the signal component such that the output signal applied to the device during the test is automatically changed;

wherein the output signal is pre-defined in advance of the test, such that a sequence of waveform slices are selectable so as to constitute the output signal and events that trigger switching from one slice of the sequence to another slice of the sequence during the test.

2. The system of claim 1, the device is one of a semiconductor device, a circuit board, an integrated circuit, and a portable computing device.

3. The system of claim 1, the signal component generates the output signal by assembling the output signal with one or more signal slices.

4. The system of claim 1, the signal component alters the output signal by changing characteristics of the output signal according to at least one of frequency, amplitude, and composition based on signal slices.

5. The system of claim 1, the signal component is an arbitrary waveform generator and the monitor component is a data acquisition system.

6. The system of claim 1, the output signal is changed in response to the one or more parameters measured by the monitor component.

7. The system of claim 1, wherein initial parameters of the output signal are defined, and thereafter, the output signal is adjusted automatically by the system according to changes in the one or more parameters of the device.

8. The system of claim 1, the output signal is generated from at least one of a positive ramp signal, a negative ramp signal, and a DC signal.

9. The system of claim 1, further comprising a memory that stores standard waveforms that are used to generate the output signal.

10. A system that facilitates characterizing electrical behavior of a cell, comprising:

a arbitrary waveform generator component that generates an output waveform for application to the cell;

a data acquisition component that monitors at least one of voltage across the cell and current through the cell to determine a change in one or more electrical parameters of the cell while the cell is being tested, a monitor component communicates with a signal component such that the signal component changes the output waveform in response to a change in the electrical behavior of the cell; and

the output signal is specified prior to the test, by selecting a series of waveform slices that form the output signal and events that trigger changing from one slice of the series to another slice of the series while conducting the test.

11. The system of claim 10, the voltage and current are digitized for further processing and display.

12. A computer that employs the system of claim 10.

13. The system of claim 10, wherein initial parameters of the output waveform are defined according to stored waveforms that include at least one of a positive ramp signal, a negative ramp signal, and a DC signal, such that the chosen series of waveform slices of the stored waveforms constitute the output waveform.

14. The system of claim 13, defines events that trigger switching from one slice of the sequence to another slice of the sequence are further defined during the test, and thereafter, the output waveform is adjusted automatically by the system according to changes in the one or more parameters of the cell.

15. A system that facilitates testing a device, comprising:

a housing;

a waveform generator component located in the housing that generates an output signal for application to the device;

a data acquisition component located in the housing that monitors one or more parameters of the device while the device is being tested, and communicates with the waveform generator component such that the waveform generator component changes the output signal being applied to the device during the test;

a trigger component located in the housing that communicates with the data acquisition component to detect a change in a state of the device during the test;

a user interface that allows interaction with a user for configuration and presentation of test information; and

the output signal is specified ahead of the test, by selecting a series of slices that will make up the output signal and events that trigger switching from one slice of the series to another slice of the series during the test.

16. The system of claim 15, the user interface is part of an external computer that communicates with components of the housing for the configuration and the presentation of the test information.

17. The system of claim 15, further comprising a display as part of the housing for presenting test information.

18. The system of claim 15, further comprising an oscilloscope in the housing that facilitates the processing and presentation of the one or more parameters of the device based on trigger events detected by the trigger component.

19. The system of claim 15, the user interface is included in the housing.

20. A method of testing a device, comprising:

defining an output signal in advance of the test;

providing a set of base waveforms in a memory;

defining initial settings of a test waveform to be applied to the device;

slicing the set of base waveforms into waveform slices;

assembling selected waveform slices in a sequence to form the test waveform;

choosing events that trigger switching from one slice of a sequence to another slice of a sequence during test;

applying the test waveform to the device during a test phase; and

changing the test waveform in response to a measured change in the device.

21. The method of claim 20, the act of changing further comprises at least one of the acts of,

changing an order of the slices;

adding a slice;

removing a slice;

altering a frequency of the waveform; and

altering a magnitude of the waveform.

22. The method of claim 20, further comprising defining threshold-based triggers according to a magnitude of a voltage and a current.

23. The method of claim 20, further comprising calculating a value for a waveform slice on-the-fly during the test when the value is previously unknown.

24. The method of claim 20, the set of base waveforms includes a baseline waveform that facilitates a baseline slice that serves as a reference for the test waveform.

25. The method of claim 20, the test waveform is a mixed signal.

26. The method of claim 20, one of the waveform slices is a combination of two or more of the base waveforms.

27. The system of claim 20, the set of base waveforms includes a baseline waveform that facilitates a baseline slice that serves as a reference for the test waveform.

28. A system that facilitates testing a cell, comprising:

means for defining an output signal in advance of the test;

means for providing a set of base waveforms in a memory;

means for slicing the set of base waveforms into waveform slices;

means for determining a sequence of the waveform slices that constitute a test waveform;

means for selecting one or more events that trigger switching from one slice to a next slice;

means for assembling selects ones of the waveform slices to form the test waveform;

means for applying the test waveform to the cell during a test phase; and

means for changing the test waveform in response to a measured change in the cell during the test phase.

29. The system of claim 28, further comprising means for defining threshold-based triggers according to a magnitude of a voltage and a current.

30. The system of claim 28, further comprising means for calculating a value for a waveform slice on-the-fly during the test when the value is previously unknown.