Light emitting device methods

• US 7,074,631 B2
• Filed: 03/05/2004
• Issued: 07/11/2006
• Est. Priority Date: 04/15/2003
• Status: Active Grant

• Current Assignee: Formosa Epitaxy Incorporated (Epistar Corporation)
• Original Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Inventors: Erchak, Alexei A., Brown, Michael Gregory, Graff, John W., Duncan, Scott W., Minsky, Milan S.
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US10/794,452
• Publication Number:
  US 20040259285A1
• Time in Patent Office: 858 Days
• Field of Search: 216/41, 216 47- 50, 257/14, 257 79-103, 430/272.1, 430314-317, 438/22, 438 28- 32, 438/34, 438/35, 438/39, 438/42, 438/725, 438/736, 438/760, 438761-763, 438/780, 438/781, 438/949, 438/950, 438/956
• US Class Current: 438/22
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer
• CPC Class Codes: Y10S 438/956 Making multiple wavelength emissive device

Abstract

A method includes disposing a planarization layer on a surface of a layer of semiconductor material and disposing a lithography layer on a surface of the planarization layer. The method also includes performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern.

Claims

1. A method of making a light-emitting device, the method comprising:

disposing a planarization layer on a surface of a layer of semiconductor material;

disposing a lithography layer on a surface of the planarization layer;

performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern;

after removing portions of the lithography and planarization layers, depositing a material on exposed portions of the layer of semiconductor material;

depositing the material on an exposed upper surface of the lithography layer;

removing the portions of lithography layer having the material deposited thereon; and

removing portions of the layer of semiconductor material that do not have the material deposited thereon to form the pattern in the surface of the layer of semiconductor material.

2. The method of claim 1, wherein performing nanolithography includes forming indentations in the lithography layer.

3. The method of claim 2, further comprising heating the lithography layer while forming the indentations in the lithography layer.

4. The method of claim 3, wherein the lithography layer is cooled after forming the indentations.

5. The method of claim 2, further comprising UV-curing the lithography layer while forming the indentations in the lithography layer.

6. The method of claim 2, wherein the indentations from the lithography layer correspond to the portion of the lithography layer removed during nanolithography.

7. The method of claim 1, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

8. The method of claim 7, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

9. The method of claim 8, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

10. The method of claim 1, further comprising removing the portions of the planarization layer corresponding to the portions of the lithography layer having the material deposited thereon.

11. The method of claim 1, wherein the material comprises a metal.

12. The method of claim 11, wherein the material comprises at least one metal selected from the group consisting of aluminum, nickel, titanium and tungsten.

13. The method of claim 1, wherein performing nanolithography includes forming indentations in the lithography layer, and the method further comprises coating at least some of the indentations in the lithography layer with an etch resistant material.

14. The method of claim 13, wherein the etch resistant material is disposed on the surface of the lithography layer, and the etch resistant material is then etched to expose an upper surface of the lithography layer while keeping some of the etch resistant material in the indentations in the lithography layer.

15. The method of claim 14, wherein the etch resistant material is spin coated onto the lithography layer.

16. The method of claim 14, wherein the etch resistant material comprises a silicon doped polymer.

17. The method of claim 14, wherein the portions of the lithography layer that are not coated with the etch resistant material correspond to the portion of the lithography layer removed during nanolithography.

18. The method of claim 17, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

19. The method of claim 18, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

20. The method of claim 19, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

21. The method of claim 1, further comprising, after performing nanolithography, removing remaining portions of the planarization layer and remaining portions of the lithography layer.

22. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, disbonding the layer of semiconductor material from a substrate.

23. The method of claim 22, wherein disbonding the layer of semiconductor material from the substrate includes a laser liftoff process.

24. The method of claim 22, wherein disbonding the layer of semiconductor material includes etching the substrate.

25. The method of claim 22, wherein disbonding the layer of semiconductor material includes lapping the substrate.

26. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, etching the surface of the layer of semiconductor material.

27. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, performing chemical-mechanical polishing on the surface of the layer of semiconductor material.

28. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, lapping the surface of the layer of semiconductor material.

29. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, polishing the surface of the layer of semiconductor material.

30. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, grinding the surface of the layer of semiconductor material.

31. The method of claim 1, further comprising, after performing nanolithography, depositing an electrical contact on the surface of the layer of semiconductor material.

32. The method of claim 1, wherein the semiconductor material comprises a III–

V semiconductor material.

33. The method of claim 32, wherein the III–

V semiconductor material is doped.

34. The method of claim 33, wherein the III–

V semiconductor material is n-doped.

35. The method of claim 1, wherein the semiconductor material is selected from the group consisting of n-doped GaN, n-doped AlInGaN, n-doped AlGaN, n-doped InGaN and combinations thereof.

36. The method of claim 1, wherein the lithography layer comprises a polymer.

37. The method of claim 36, wherein the polymer comprises a UV-curable polymer.

38. The method of claim 37, wherein the polymer comprises a high-viscosity formable polymer.

39. The method of claim 1, wherein the lithography layer is at least about one nanometer thick.

40. The method of claim 1, wherein the lithography layer is at most about one micron thick.

41. The method of claim 1, wherein the planarization layer comprises a polymer.

42. The method of claim 1, wherein the planarization layer is at least about 100 nanometers thick.

43. The method of claim 1, wherein the planarization layer is at most about five microns thick.

44. The method of claim 1, wherein the layer of semiconductor material comprises a layer of n-doped semiconductor material, and the layer of semiconductor material is supported by a layer of p-doped semiconductor material and an active region of semiconductor material, the active region of semiconductor material being between the layer of n-doped semiconductor material and the layer of p-doped semiconductor material.

45. The method of claim 1, wherein the light-emitting device is selected from the group consisting of light-emitting diodes, lasers, optical amplifiers, and combinations thereof.

46. The method of claim 1, wherein the light-emitting device comprises a light emitting diode.

47. The method of claim 1, wherein the light-emitting device is selected from the group consisting of OLEDs, flat surface-emitting LEDs, HBLEDs, and combinations thereof.

48. The method of claim 1, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a periodic pattern.

49. The method of claim 1, wherein the surface of the layer of semiconductor material is rough.

50. The method of claim 1, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a nonperiodic pattern.

51. The method of claim 1, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per square centimeter.

52. The method of claim 1, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per 6.25 square centimeters.

53. The method of claim 1, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has an RMS roughness of at most about 50 nanometers.

54. The method of claim 1, wherein, before performing nanolithography, the planarization layer, the lithography layer and the layer of semiconductor material are in the form of a wafer.

55. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, performing at least one process selected from the group consisting of etching the surface of the layer of semiconductor material, chemical-mechanical polishing the surface of the layer of semiconductor material, lapping the surface of the layer of semiconductor material, polishing the surface of the layer of semiconductor material, and grinding the surface of the layer of semiconductor material.

56. The method of claim 1, further comprising, prior to depositing the lithography layer, flattening an upper surface of the planarization layer.

57. The method of claim 1, wherein the material comprises a metal.

58. The method of claim 57, wherein the material comprises at least one metal selected from the group consisting of aluminum, nickel, titanium and tungsten.

59. A method of making a light-emitting device, the method comprising:

providing an article that comprises a layer of semiconductor material, a planarization layer supported by the layer of semiconductor material, and a lithography layer supported by the planarization layer; and

performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer, and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern;

after removing portions of the lithography and planarization layers, depositing a material on exposed portions of the layer of semiconductor material;

depositing the material on an exposed upper surface of the lithography layer;

removing the portions of lithography layer having the material deposited thereon; and

removing portions of the layer of semiconductor material that do not have the material deposited thereon to form the pattern in the surface of the layer of semiconductor material.

60. The method of claim 59, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

61. The method of claim 60, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

62. The method of claim 59, wherein the article further comprises an etch mask layer.

63. The method of claim 62, wherein the etch mask layer is between the layer of semiconductor material and the planarization layer.

64. The method of claim 62, wherein performing nanolithography removes at least a portion of the etch mask layer.

65. The method of claim 59, further comprising removing the portions of the planarization layer corresponding to the portions of the lithography layer having the material deposited thereon.

66. The method of claim 59, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

67. The method of claim 66, wherein performing nanolithography includes forming indentations in the lithography layer, and the method further comprises coating at least some of the indentations in the lithography layer with an etch resistant material.

68. The method of claim 67, wherein the etch resistant material is disposed on the surface of the lithography layer, and the etch resistant material is then etched to expose an upper surface of the lithography layer while keeping some of the etch resistant material in the indentations in the lithography layer.

69. The method of claim 67, wherein the etch resistant material is spin coated onto the lithography layer.

70. The method of claim 67, wherein the etch resistant material comprises a silicon doped polymer.

71. The method of claim 70, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

72. The method of claim 71, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

73. The method of claim 67, wherein the portions of the lithography layer that are not coated with the etch resistant material correspond to the portion of the lithography layer removed during nanolithography.

74. The method of claim 73, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

75. The method of claim 59, further comprising, before supporting the planarization layer with the layer of semiconductor material, disbonding the layer of semiconductor material from a substrate.

76. The method of claim 75, wherein disbonding the layer of semiconductor material from the substrate includes a laser liftoff process.

77. The method of claim 75, wherein disbonding the layer of semiconductor material includes etching the substrate.

78. The method of claim 75, wherein disbonding the layer of semiconductor material includes lapping the substrate.

79. The method of claim 59, further comprising, before supporting the planarization layer with the layer of semiconductor material, etching the surface of the layer of semiconductor material.

80. The method of claim 59, further comprising, before supporting the planarization layer with the layer of semiconductor material, performing chemical-mechanical polishing on the surface of the layer of semiconductor material.

81. The method of claim 59, further comprising, before supporting the planarization layer with the layer of semiconductor material, lapping the surface of the layer of semiconductor material.

82. The method of claim 59, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, polishing the surface of the layer of semiconductor material.

83. The method of claim 59, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, grinding the surface of the layer of semiconductor material.

84. The method of claim 59, wherein the semiconductor material comprises a III–

V semiconductor material.

85. The method of claim 84, wherein the III–

V semiconductor material is doped.

86. The method of claim 85, wherein the III–

V semiconductor material is n-doped.

87. The method of claim 59, wherein the semiconductor material is selected from the group consisting of n-doped GaN, n-doped AlInGaN, n-doped AlGaN, n-doped InGaN and combinations thereof.

88. The method of claim 59, wherein the light-emitting device is selected from the group consisting of light-emitting diodes, lasers, optical amplifiers, and combinations thereof.

89. The method of claim 59, wherein the light-emitting device comprises a light emitting diode.

90. The method of claim 59, wherein the light-emitting device is selected from the group consisting of OLEDs, flat surface-emitting LEDs, HBLEDs, and combinations thereof.

91. The method of claim 59, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a periodic pattern.

92. The method of claim 59, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a nonperiodic pattern.

93. The method of claim 59, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per square centimeter.

94. The method of claim 59, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per 6.25 square centimeters.

95. The method of claim 59, wherein, before supporting the planarization layer with the layer of semiconductor material, the surface of the layer of semiconductor material has an RMS roughness of at most about 50 nanometers.

96. The method of claim 95, further comprising heating the lithography layer while forming the indentations in the lithography layer.

97. The method of claim 96, wherein the lithography layer is cooled after forming the indentations.

98. The method of claim 59, further comprising, prior to depositing the lithography layer, flattening an upper surface of the planarization layer.

99. A method of making a light-emitting device, the method comprising:

disposing a planarization layer on a surface of a layer of semiconductor material;

disposing a lithography layer on a surface of the planarization layer; and

performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern;

wherein performing nanolithography includes forming indentations in the lithography layer, and the method further comprises coating at least some of the indentations in the lithography layer with an etch resistant material.

100. The method of claim 99, wherein the etch resistant material is disposed on the surface of the lithography layer, and the etch resistant material is then etched to expose an upper surface of the lithography layer while keeping some of the etch resistant material in the indentations in the lithography layer.

101. The method of claim 100, wherein the etch resistant material is spin coated onto the lithography layer.

102. The method of claim 100, wherein the etch resistant material comprises a silicon doped polymer.

103. The method of claim 100, wherein the portions of the lithography layer that are not coated with the etch resistant material correspond to the portion of the lithography layer removed during nanolithography.

104. The method of claim 103, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

105. The method of claim 104, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

106. The method of claim 105, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

107. The method of claim 99, further comprising UV-curing the lithography layer while forming the indentations in the lithography layer.

108. The method of claim 99, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a periodic pattern.

109. The method of claim 99, wherein the surface of the layer of semiconductor material is rough.

110. The method of claim 99, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a nonperiodic pattern.

111. A method of making a light-emitting device, the method comprising:

disposing a planarization layer on a surface of a layer of semiconductor material;

disposing a lithography layer on a surface of the planarization layer;

performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern;

after removing portions of the lithography and planarization layers, depositing a material on exposed portions of the layer of semiconductor material;

depositing the material on an exposed upper surface of the lithography layer;

removing the portions of lithography layer having the material deposited thereon; and

removing the portions of the planarization layer corresponding to the portions of the lithography layer having the material deposited thereon.

112. The method of claim 111, wherein the material comprises a metal.

113. The method of claim 112, wherein the material comprises at least one metal selected from the group consisting of aluminum, nickel, titanium and tungsten.

114. The method of claim 111, wherein the material is spin coated onto the lithography layer.

115. The method of claim 111, wherein the material comprises a silicon doped polymer.

116. The method of claim 111, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a periodic pattern.

117. The method of claim 111, wherein the surface of the layer of semiconductor material is rough.

118. The method of claim 111, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a nonperiodic pattern.