Surface micromachining process for manufacturing electro-acoustic transducers, particularly ultrasonic transducers, obtained transducers and intermediate products

• US 7,074,634 B2
• Filed: 05/09/2002
• Issued: 07/11/2006
• Est. Priority Date: 05/09/2001
• Status: Expired due to Fees

• Current Assignee: Esaote SpA, Consiglio Nazionale Delle Ricerche (Repubblica Italiana), Universita Degli Studi Di Cagliari
• Original Assignee: Esaote SpA, Consiglio Nazionale Delle Ricerche (Repubblica Italiana), Universita Degli Studi Di Cagliari
• Inventors: Caliano, Giosué, Memmi, Daniele, Pappalardo, Massimo, Cianci, Elena, Foglietti, Vittorio
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US10/476,254
• Publication Number:
  US 20040180466A1
• Time in Patent Office: 1,524 Days
• Field of Search: 438 27- 29, 438/34, 438/50, 438/57, 438/66, 438/68, 438/72, 438/73, 438/460, 438/53
• US Class Current: 438/50
• CPC Class Codes: H04R 19/00 Electrostatic transducers

Abstract

A surface micromachining process for manufacturing Electro-acoustic transducers, particularly ultrasonic transducers, the transducers comprising a silicon semiconductor substrate (1), on an upper surface of which one or more membranes (18) of resilient materials are supported by a structural layer (11) of insulating material, rigidly connected to the semiconductor substrate (1), the resilient material having a Young'"'"'s modulus not lower than 50 GPa, the membranes (18) being metallised, the transducers including one or more lower electrodes (23, 25), rigidly connected to the semiconductor substrate. The process is characterised in that the structural layer (11) includes silicon monoxide. The invention further relates to an Electro-acoustic transducer, particularly an ultrasonic transducer, characterised in that the insulating material of the structural layer (11) is silicon monoxide. The invention also relates to an intermediate product for utilisation in the process for realising Electro-acoustic transducers, particularly ultrasonic transducers.

Claims

1. A surface micromachining process for manufacturing Electroacoustic transducers, particularly ultrasonic transducers, said transducers comprising a silicon semiconductor substrate (1), on an upper surface of which one or more membranes (18) of resilient materials are supported by a structural layer (11) of insulating material, rigidly connected to said silicon semiconductor substrate (1), said resilient material having a Young'"'"'s modulus not lower than 50 GPa, said membranes (18) being metallised, said transducers including one or more lower electrodes (23, 25), rigidly connected to said silicon semiconductor substrate (1), the process comprising the following steps:

A. providing said silicon semiconductor substrate (1),

B. realising an intermediate product comprising;

a sacrificial layer (8, 8′

), and

a structural layer (11) of insulating material,

rigidly connected to an upper surface of said silicon semiconductor substrate (1), the surfaces of said sacrificial layer (8, 8′

) and of said structural layer (11) not in contact with said silicon semiconductor substrate (1) being substantially co-planar,

C. depositing a layer (15) of said resilient material on said sacrificial layer (8, 8′

) and on said structural layer (11), and

D. releasing said membranes (18) of said resilient material by removing said sacrificial layer (8, 8′

) from the product obtained according to said step C.,

said process being characterised in that said structural layer (11) includes silicon monoxide.

2. A process according to claim 1, characterised in that all of the steps of the process are carried out at temperatures not higher than 600°

C.

3. A process according to claim 2, characterised in that all of the steps of the process are carried out at temperatures not higher than 530°

C.

4. A process according to claim 1, characterised in that said resilient material has a value of the Young'"'"'s modulus not lower than 100 GPa.

5. A process according to claim 4, characterised in that said resilient material comprises silicon nitride.

6. A process according to claim 4, characterised in that said resilient material comprises crystalline silicon.

7. A process according to claim 1, characterised in that said sacrificial material (8′

) comprises chromium.

8. A process according to claim 1, characterised in that said sacrificial material (8) comprises an organic polymer selected among the group consisting of polyamides and polymers of benzocyclobutene and its derivatives.

9. A process according to claim 8, characterised in that said organic polymer comprises polyamide.

10. A process according to claim 9, characterised in that said polyamide comprises N-methyl-2-pyrolidone.

11. A process according to claim 1, characterised in that said step D comprises the following successively ordered sub-steps:

D.1 realising one or more apertures or vias (16) on said layer (15) of resilient material, adapted to enable accessing the sacrificial layer (8) from outside, and

D.2 thermally treating by annealing the product obtained according to said step C.

12. A process according to claim 9, characterised in that, during execution of said substep D.2, the product obtained according to said step C is heated to a temperature in the range of 490°

C. to 530°

C.

13. A process according to claim 11, characterised in that said sub-step D.2 has a duration adapted to completely eliminate the organic polymer existing in the product obtained according to said step C.

14. A process according to claim 11, characterised in that said step D further comprises, indifferently before or after said sub-step D.1 or D.2, the following sub-step:

D.3 chemically etching said sacrificial layer.

15. A process according to claim 14, characterised in that said sub-step D.3 comprises imaging the product in a wet etching solution for etching chromium.

16. A process according to claim 14, characterised in that said sub-step D.3 comprises imaging the product obtained according to said step C in a solution comprising sulphuric acid (H₂SO₄).

17. A process according to claim 16, characterised in that said solution utilised in said sub-step D.3 further comprises hydrogen peroxide (H₂O₂).

18. A process according to claim 17, characterised in that said solution utilised in said sub-step D.3 is a solution 7:

3 of sulphuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂).

19. A process according to claim 14, characterised in that, when said sub-step D.3 is subsequent to said sub-step D.2, said step D further comprises, after said sub-step D.3, the following sub-step:

D.4 thermally treating by annealing the product obtained according to said step D.

20. A process according to claim 19, characterised in that, during execution of said sub-step D.4, the product obtained according to said step C is heated to a temperature in the range of 490°

C. to 530°

C.

21. A process according to claim 11, characterised in that the total duration of the annealing operation for the product obtained according to said step C is adapted to make the intrinsic compression stress of the membranes (18) no higher than 10 MPa.

22. A process according to claim 21, characterised in that the total duration of the annealing operation for the product obtained according to said step C is adapted to make the intrinsic tensile stress of the membranes (18) comprised in the range of 10 MPa to 50 MPa.

23. A process according to claim 11, characterised in that said vias (16) are external to the locations of said membranes (18) and are positioned at a distance therefrom adapted to introduce substantially negligible stress gradients, said sacrificial layer (8) comprising channels (7) to connect the positions of said vias (16) to the locations of said membranes (18).

24. A process according to claim 7, characterised in that said step B comprises the following successively ordered sub-steps:

B.1 depositing a chromium comprising layer (28) on said upper surface of said silicon semiconductor substrate (1),

B.2 defining configurations or patterns in said chromium comprising layer (28) by realising cavities in said chromium comprising layer (28), and

B.3 filling said cavities in said chromium comprising layer (28) by depositing silicon monoxide therein.

25. A process according to claim 8, characterised in that said step B comprises the following successively ordered sub-steps:

B.1 applying a layer (2) comprising said organic polymer upon said upper surface of said silicon semiconductor substrate (1),

B.2 defining configurations or patterns in said layer (2) comprising said organic polymer by realising cavities (10) in said in said layer comprising said organic polymer, and

B.3 filling said cavities (10) in said layer (2) comprising said organic polymer by depositing silicon monoxide therein.

26. A process according to claim 24, characterised in that, during said sub-step B.3, the silicon monoxide is deposited by thermal evaporation.

27. A process according to claim 24, characterised in that said sub-step B.2 comprises an optical lithographic process performed on said chromium comprising layer (28) by utilising a masking layer of photographically patterned optical resist and a wet chemical etching of the chromium.

28. A process according to claim 25, characterised in that said sub-step B.2 comprises a dry reactive ion etching (RIE) operation performed on said layer (2) comprising said organic polymer by utilising a masking layer (9) of photolithographically patterned optical resist.

29. A process according to claim 27, characterised in that said step B further comprises, after said sub-step B.3, the following sub-steps:

B.4 chemically etching said silicon monoxide by utilising a wet etching process,

B.5 removing said optical resist.

30. A process according to claim 27, characterised in that said step B further comprises, after said sub-step B.3, the following sub-step:

B.4 removing the silicon monoxide deposited upon said optical resist by means of a lift off process.

31. A process according to claim 30, characterised in that said sub-step B.4 comprises dissolving said optical resist by means of an acetone and ultrasound dissolving process.

32. A process according to claim 8, characterised in that said step B comprises the following successively ordered sub-steps:

B.1 depositing a silicon monoxide comprising layer on said upper surface of the semiconductor substrate (1),

B.2 defining configurations or patterns (11) in said silicon monoxide comprising layer,

B.3 applying a layer (2) comprising said organic polymer upon said upper surface of the semiconductor substrate (1), provided with silicon monoxide,

B.4 performing a chemical-mechanical polishing operation adapted to realise said intermediate product.

33. A process according to claim 32, characterised in that during said sub-step B.1, the silicon monoxide is deposited by thermal evaporation.

34. A process according to claim 32, characterised in that said sub-step B.2 comprises a dry reactive ion etching (RIE) operation performed on said silicon monoxide comprising layer by utilising a masking layer of photolithographically patterned optical resist.

35. A process according to claim 1, characterised in that, during said step C, said resilient material is deposited by a plasma enhanced chemical vapour deposition process (PECVD).

36. A process according to claim 11, characterised in that it further comprises, after said step D, the following step:

E. closing said vias (16) by

deposition of silicon monoxide adapted to fill up said vias (16),

optical lithography, and

RIE etching of the silicon monoxide deposited on said membranes (18).

37. A process according to claim 36, characterised in that during said step E, said silicon monoxide is deposited by thermal evaporation.

38. A process according to claim 1, characterised in that it further comprises, before said step B, the following step:

F. realising a lower electrode (25) on the upper surface of the semiconductor substrate (1) in positions corresponding to each area in which said membranes (18) are realised during said step D.

39. A process according to claim 38, characterised in that said step F comprises the following sub-steps:

F.1 depositing an insulating layer (26) on the upper surface of the semiconductor substrate (1),

F.2 depositing a conductive layer upon said insulating layer (26),

F.3 defining configurations or patterns in said conductive layer.

40. A process according to claim 39, characterised in that said insulating layer (26) comprises thermal silicon dioxide SiO₂, said conductive layer comprises evaporation deposited chromium, and said sub-step F.3 comprises an optical lithographic process performed on said conductive layer by utilising a masking layer formed by a photolithographically patterned optical resist and a chemical wet etching of the chromium.

41. A process according to claim 38, characterised in that said step F further realises a film (27) for protection of said lower electrodes (25).

42. A process according to claim 41, characterised in that said protection film (27) is realised by growing a film of silicon nitride sIN by means of a PECVD technique.

43. A process according to claim 1, characterised in that it further comprises the following step:

F. realising one or more lower electrodes (23) by metallisation of a lower surface of said siliconsemiconductor substrate (1).

44. A process according to claim 1, characterised in that it further comprises the following step:

G. metallising said membranes (18).

45. A process according to claim 1, characterised in that said silicon semiconductor substrate (1) is a p-type doped silicon substrate having a resistivity no higher than 1 Ω

.cm, preferably no higher than 2 Ω

.cm.

46. A process according to claim 1, characterised in that said silicon monoxide comprising structural layer (11) has a thickness in the range of 100 nm to 1000 nm, preferably in the range of 400 nm to 600 nm, and in that said membranes (18) of said resilient material have a thickness no higher than 1000 nm, preferably no higher than 600 nm.