Gate material for semiconductor device fabrication

• US 7,074,655 B2
• Filed: 09/28/2005
• Issued: 07/11/2006
• Est. Priority Date: 10/22/2002
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Lochtefeld, Anthony J., Currie, Matthew T., Antoniadis, Dimitri
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US11/237,175
• Publication Number:
  US 20060024869A1
• Time in Patent Office: 286 Days
• Field of Search: 438/149, 438/150, 438/198, 438/933, 438/938, 257/190, 257/191, 257/192, 257/347, 257/350, 257/351
• US Class Current: 438/149
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

Claims

1. A method for forming a structure, the method comprising:

forming a gate of a transistor over a substrate, the gate defining a channel therebelow;

introducing a plurality of dopants into the substrate proximate the channel to define a source and drain; and

heating the substrate to a temperature for a time to activate the plurality of dopants,

wherein the gate includes a depletion region having a thickness less than approximately 20 Angstroms, and at least one of the temperature and the time is sufficiently low so that diffusion of the plurality of dopants beyond the source and the drain is sufficiently low such that an off current of the transistor is low.

2. The method of claim 1, wherein the channel comprises a strained semiconductor.

3. The method of claim 1, wherein forming the gate comprises depositing a semiconductor layer over the substrate, forming a metal layer over the semiconductor layer, and heating the substrate such that at least a portion of the semiconductor layer reacts with the metal layer to form a metal-semiconductor alloy.

4. The method of claim 3, further comprising introducing a plurality of dopants into the gate.

5. The method of claim 3, wherein substantially all of the semiconductor layer reacts with the metal to form the metal-semiconductor alloy.

6. The method of claim 3, wherein the metal comprises Ni.

7. The method of claim 6, wherein the substrate is heated by at least one of flash annealing and laser annealing and the time is less than 1 second.

8. The method of claim 7, wherein the temperature is chosen from a range of 900°

C. –

1350°

C.

9. The method of claim 1, wherein after heating the substrate, an abruptness of a dopant concentration in at least one of the source and the drain is greater than approximately 2 nanometers per decade.

10. The method of claim 9, wherein the abruptness is greater than approximately 4 nanometers per decade.

11. The method of claim 1, wherein the gate consists essentially of metal.

12. The method of claim 11, wherein the metal consists essentially of a single metallic element.

13. The method of claim 11, wherein the metal consists essentially of at least two metallic elements.

14. The method of claim 1, wherein at least one of the source and drain comprises an element other than Si.

15. The method of claim 14, wherein the element comprises Ge.

16. The method of claim 1, wherein at least one of the source and the drain comprises a strained semiconductor material.

17. The method of claim 16, wherein the strained semiconductor material is compressively strained.

18. The method of claim 1, wherein the strained semiconductor material comprises at least one of SiGe and Ge.

19. The method of claim 1, wherein the off current is less than 10⁻

6 Amperes per micrometer.

20. The method of claim 19, wherein the off current is less than 10⁻

9 Amperes per micrometer.

21. A structure comprising:

a substrate;

an n-type metal-oxide semiconductor field-effect transistor disposed over the substrate including;

a first source and a first drain, defining a first channel therebetween and each of the first source and first drain comprising n-type dopants,

a first gate disposed above the first channel, the first gate having a first workfunction and comprising a first metal, and

a first gate dielectric layer disposed between the first gate and the first channel; and

a p-type metal-oxide semiconductor field-effect transistor disposed over the substrate including;

a second source and a second drain, defining a second channel therebetween and each of the second source and second drain comprising p-type dopants;

a second gate disposed above the second channel, the second gate having a second workfunction and comprising a second metal; and

a second gate dielectric layer disposed between the second gate and the second channel,

wherein the first workfunction is substantially different from the second workfunction, and at least one of the first channel and the second channel comprises a strained semiconductor.

22. The structure of claim 21, wherein the first channel and the second channel each comprises a strained semiconductor.

23. The structure of claim 21, wherein at least one of the first metal and the second metal comprises at least one of molybdenum, titanium, tantalum, tungsten, iridium, cobalt, and platinum.

24. The structure of claim 21, wherein at least one of the first metal and the second metal comprises nickel.

25. The structure of claim 21, wherein at least one of the first gate and the second gate consists essentially of a metal-semiconductor alloy.

26. The structure of claim 21, wherein an abruptness of a dopant concentration in at least one of the first source, the first drain, the second source, and the second drain is greater than approximately 2 nanometers per decade.

27. The structure of claim 26, wherein the abruptness is greater than approximately 4 nanometers per decade.

28. The structure of claim 21, wherein at least one of the first source, the first drain, the second source, and the second drain comprises a second strained semiconductor.

29. The structure of claim 28, wherein the second strained semiconductor is compressively strained.

30. The structure of claim 28, wherein the second strained semiconductor comprises at least one of SiGe and Ge.

31. The structure of claim 21, wherein the strained semiconductor comprises tensilely strained Si.