In situ determination of resistivity, mobility and dopant concentration profiles

• US 7,078,919 B2
• Filed: 08/26/2004
• Issued: 07/18/2006
• Est. Priority Date: 08/27/2003
• Status: Active Grant

• Current Assignee: Active Layer Parametrics, Inc.
• Original Assignee: Simon A. Prussin
• Inventors: Prussin, Simon A.
• Primary Examiner(s): DEB, ANJAN K
• Application Number:
  US10/927,945
• Publication Number:
  US 20050052191A1
• Time in Patent Office: 691 Days
• Field of Search: 324/719, 324/691, 324/71.5
• US Class Current: 324/719
• CPC Class Codes: G01N 27/041 of a solid body
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

The present invention provides techniques for an in-situ measurement of resistivity profiles and dopant concentration distributions in semiconductor structures, such as shallow junctions. A substrate with a resistor test structure having a conduction circuit may be placed at a measurement station, surface layers may be successively removed from the conduction circuit at the measurement station, a sheet resistance of the conduction circuit may be measured at the measurement station after the removal of each surface layer to generate a plurality of sheet resistance measurements, and the resistivity profile may be calculated from the plurality of sheet resistance measurements.

Claims

1. A method of determining the resistivity profile in a pn structure or in the silicon surface layer on a SOI (silicon on insulator) structure comprising the steps of:

placing a substrate with a resistor test structure having a conduction circuit including a semiconductor layer on said pn or SOI structure at a measurement station;

converting successively deeper sublayers of the semiconductor layer from the conduction circuit into a surface oxide by anodic oxidation at the measurement station;

measuring a sheet resistance of the conduction circuit at the measurement station after converting each sublayer and without removing the surface oxide to generate a plurality of sheet resistance measurement; and

calculating the resistivity profile from the plurality of sheet resistance measurements.

2. The method of claim 1, further comprising measuring an initial sheet resistance of the conduction circuit prior to converting any sublayers.

3. The method of claim 1, wherein measuring the sheet resistance is performed alternately with the anodic oxidation.

4. The method of claim 1, wherein anodic direct current is applied between a cathode and the test structure with a constant current source, and an incremental forming voltage is measured and used to determine a thickness of a converted sublayer.

5. The method of claim 1, wherein the anodic oxidation is confined to a small area where the test structure is located.

6. The method of claim 5, wherein the resistor test structure is a cross van der Pauw resistor, and wherein the anodic oxidation is confined to the intersection of the arms of the cross van der Pauw resistor.

7. The method of claim 6, wherein the resistance is measured by applying an alternating current through two arms of the van der Pauw resistor and measuring the voltage drop across the contacts on the opposite two arms.

8. The method of claim 1, wherein measuring the sheet resistance measurement is performed without removing an overlying electrolyte.

9. The method of claim 8, wherein anodic oxidation is paused during measuring the sheet resistance.

10. The method of claim 1, further comprising calculating a dopant concentration distribution of the pn structure or silicon surface layer from the resistivity profile.

11. The method of claim 10, wherein the dopant concentration distribution is calculated from the resistivity profile on the basis of specific mobility data.

12. The method of claim 10, wherein the dopant concentration distribution is calculated from the resistivity profile on the basis of A.S.T.M. Standard F723.

13. The method of claim 1, wherein converting sublayers of the conduction circuit is carried out non-destructively on a production wafer such that the production wafer can be returned to the production process.

14. The method of claim 1, further comprising applying a magnetic field to the resistor test structure and measuring Hall sheet coefficients.

15. The method of claim 14, further comprising calculating a mobility profile from the Hall sheet coefficients.

16. The method of claim 1, wherein the semiconductor layer of the resistor test structure is electrically isolated from a remainder of the semiconductor layer of the substrate.

17. The method of claim 1, wherein the semiconductor layer comprises a silicon substrate.

18. A method of processing a substrate, comprising:

forming a test structure having an electrically isolated semiconductor layer at a substrate surface in a production integrated circuit substrate;

receiving the substrate at a measurement station;

converting successively deeper sublayers of the semiconductor layer from the surface of the semiconductor layer into a surface oxide by anodic oxidation at the measurement station;

making a respective sheet resistance measurement of the semiconductor layer after converting each of the sublayers and without removing the surface oxide to provide a plurality of resistance measurements;

calculating a resistivity profile for the semiconductor layer from the plurality of resistance measurements; and

after making the plurality of resistance measurements, performing at least one additional processing step on the substrate in the fabrication of integrated circuits on the substrate.

19. A method of characterizing a semiconductor layer, comprising:

receiving at a measurement station a substrate that includes a structure having an electrically isolated semiconductor layer at a substrate surface,

successively oxidizing a plurality of successively deeper semiconductor sublayers from the surface of the semiconductor layer to provide a successively deeper oxide portion on the surface of the substrate;

making a respective sheet resistance measurement of the semiconductor layer after the oxidation of each of the plurality of sublayers without removing the oxide portion and while the oxidized portion is on the surface of the substrate to provide a plurality of resistance measurements, and calculating a resistivity profile for the semiconductor layer from the plurality of resistance measurements.

20. The method of claim 19, wherein converting the sublayer of the substrate into the oxide portion includes:

positioning a receptacle over a test region of substrate including the structure, the receptacle defining an opening to the test region within a limited area;

adding an electrolyte into the receptacle positioned over the test region, the electrolyte contacting the test region in the limited area; and

applying an electric current through the electrolyte and the substrate.

21. The method of claim 20, wherein:

positioning the receptacle over the test region includes placing a seal between the substrate and the opening of the receptacle, the seal confining the electrolyte to the test region.

22. The method of claim 20, wherein the electrolyte includes an aqueous solution.

23. The method of claim 20, wherein the electrolyte includes a non-aqueous solution.

24. The method of claim 20, wherein:

the test region includes a cross of a van der Pauw resistor.

25. The method of claim 24, wherein a test structure includes the central portion and four elongated arms attached to the central portion, and wherein:

measuring the sheet resistance in the test region includes passing a test current through two adjacent arms of the test structure and measuring voltage across two of the remaining arms of the test structure.

26. The method of claim 25, wherein the test current includes an alternating current.

27. The method of claim 19, wherein:

measuring the sheet resistance includes measuring a sequence of values for the sheet resistance, each value measured for the sheet resistance at a different depth of the oxide portion.

28. The method of claim 27, further comprising:

determining a respective depth of the oxide portion for each value measured for the sheet resistance.

29. The method of claim 28, wherein:

converting the layer of the substrate into the oxide portion includes applying a predetermined electric current between a cathode and the substrate; and

determining the depth of the oxide portion includes determining the depth of the oxide portion based on a voltage drop between the cathode and the substrate.

30. The method of claim 28, further comprising:

determining one or more values of a differential resistivity based on two or more of the values measured for the sheet resistance, each value of the differential resistivity being determined for a respective depth in the substrate.

31. The method of claim 30, further comprising:

estimating a dopant distribution in the substrate based on the determined values of the differential resistivity.

32. The method of claim 19, wherein:

measuring the sheet resistance includes suspending the conversion of the semiconductor layer of the substrate into oxide while the sheet resistance is measured.

33. The method of claim 19, further comprising applying a magnetic field to the test region and measuring a Hall sheet coefficient.

34. The method of claim 33, further comprising applying a positive magnetic field to the test region and measuring a first Hall sheet coefficient and applying a negative magnetic field to the test region and measuring a second Hall sheet coefficient.

35. The method of claim 33, wherein:

measuring the Hall sheet coefficient includes measuring a sequence of values for the Hall sheet coefficient, each value measured for the Hall sheet coefficient at a different depth of the oxide portion.

36. A system for characterizing layers in semiconductor substrates, the system comprising:

a receptacle configured to receive an electrolyte and confine the received electrolyte to contact a surface of a semiconductor substrate in a limited test region;

a cathode configured to make electrical contact with the electrolyte in the receptacle;

an anodic current generator configured to pass an electric current through the cathode and the electrolyte to the substrate to successively convert deeper sublayers of a layer of the substrate into an anodic oxide layer in the test region; and

a sheet resistance meter configured to measure sheet resistance after the conversion of each of the sublayers without removing anodic oxide layer in the test region while the anodic oxide layer is on the substrate.

37. The system of claim 36, further comprising:

a controller to control the anodic current generator or the sheet resistance meter.

38. The system of claim 36, further comprising:

a first voltage meter configured to measure a voltage drop between the cathode and the substrate.

39. The system of claim 36, wherein the sheet resistance meter is configured to make electric contacts with four contact points arranged around a singly connected region of a test structure in the test region.

40. The system of claim 39, wherein the sheet resistance meter includes:

a test current generator to pass a test current through two adjacent contact points of the test structure; and

a second voltage meter to measure voltage across two of the remaining contact points of the test structure.

41. The system of claim 40, further comprising a magnet to apply a magnetic field to the test region.

42. The system of claim 41, wherein the sheet resistance meter is configured to measure a Hall sheet coefficient.

43. The system of claim 36, further comprising a controller configured to calculate a resistivity profile from the plurality of sheet resistance measurements.