High dynamic range active pixel CMOS image sensor and data processing system incorporating adaptive pixel reset

• US 7,079,178 B2
• Filed: 01/28/2002
• Issued: 07/18/2006
• Est. Priority Date: 02/20/2001
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Mangachip Semiconductor, Ltd.
• Inventors: Hynecek, Jaroslav
• Primary Examiner(s): Ho, Tuan
• Assistant Examiner(s): Vieaux, Gary C.
• Application Number:
  US10/059,546
• Publication Number:
  US 20020113886A1
• Time in Patent Office: 1,632 Days
• Field of Search: 348/302, 348/222.1, 348/312, 348/364, 348/297, 250/208.1
• US Class Current: 348/222.1
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A high Dynamic Range Active Pixel CMOS image sensor architecture has incorporated therein an adaptive pixel reset. The individual sensor pixels are reset only when accumulated charge, or the integration time exceeds certain predetermined limits. The reset is skipped when the integrated charge signal in a given pixel is low. The accumulated number of reset skips in a given time frame, together with the standard analog output, is used to calculate the sensor high DR output signal. A signal processing system is used to simultaneously process both sensor analog and digital outputs.

Claims

1. A CMOS Active Pixel image sensor, comprising:

an array of CMOS sensor pixels;

pixel addressing means, including a vertical scanner;

pixel read out means, including a horizontal scanner-buffer;

a reset register, including reset logic gates; and

a comparator, with an override capability, connected to the output of the CMOS sensor array, and said comparator compares the pixel output levels to a given reference level, wherein a digital output from the comparator is loaded into a reset register and is also supplied to a data processing system as a pixel digital sensor output.

2. The image sensor according to claim 1, wherein said image sensor includes pixels that can be individually reset at different times independently of the time of readout.

3. The image sensor according to claim 1, wherein a reset signal from the reset register is supplied to the pixels by column addressing means rather than by row addressing means.

4. The image sensor according to claim 1, wherein pixel-reset data is stored in the reset register, and is loaded into the said reset register approximately simultaneously with pixel readout.

5. The image sensor according to claim 1, wherein selected pixels are reset after the reset register loading is complete at the end of the row read out.

6. The image sensor according to claim 1, including means for skipping pixel reset if the pixel output is below a certain threshold, and where the pixel is allowed to integrate more charge before it is eventually reset.

7. The image sensor according to claim 1, including a signal processing system that is using both the analog and digital data obtained from the array of CMOS sensor pixels to form a high Dynamic Range (large n-bit word) digital pixel data.

8. The image sensor signal processing system according to claim 7, wherein the signal processing system includes pixel memory locations with the ability to store digitized sensor analog pixel outputs and several frames of pixel reset skip count outputs, and includes means to generate a pixel override output when any pixel skip counting memory locations overflows a predetermined limit.

9. The image sensor signal processing system according to claim 7, including means to compute, on a pixel-by-pixel basis, high Dynamic Range (large n-bit word) pixel data from digitized pixel analog data, and from accumulated reset skip counts.

10. The image sensor signal processing system according to claim 9, including means to process high Dynamic Range (large n-bit word) pixel data, store the data in suitable memory pixel locations, and to compress the data in a suitable compression algorithm to form pixels with smaller in-bit word sizes where m<

n.

11. A CMOS Active Pixel image sensor, comprising:

an array of CMOS sensor pixels;

pixel addressing means, including a vertical scanner;

pixel read out means, including a scanner-buffer;

a reset register, including reset logic gates;

a comparator, with an override capability, connected to the output of the CMOS sensor array, and said comparator compares the pixel output levels to a given reference level, wherein a digital output from the comparator is loaded into a reset register and is also supplied to a data processing system as a pixel digital sensor output; and

pixels in said array that can be individually reset at different times independently of time of readout.