Concurrent measurement of critical dimension and overlay in semiconductor manufacturing

• US 7,080,330 B1
• Filed: 03/05/2003
• Issued: 07/18/2006
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Ocean Semiconductor LLC (Fullbrite Capital Partners, LLC)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Morales, Carmen, Choo, Bryan, Rangarajan, Bharath, Singh, Bhanwar
• Primary Examiner(s): Lin, Sun James
• Application Number:
  US10/379,738
• Time in Patent Office: 1,231 Days
• Field of Search: 716/4, 716/19, 716/20, 716/21
• US Class Current: 716/136
• CPC Class Codes: G01N 21/4788 Diffraction for sizing particles G01N15/0205
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.

Claims

1. A system that monitors and controls a semiconductor fabrication process comprising:

a structure formed on at least a portion of a wafer matriculating through the fabrication process that facilitates concurrent measurement of one or more critical dimensions and overlay,

a measurement system that concurrently measures one or more critical dimensions and overlay by mapping the wafer into one or more grids that comprises one or more locations on which a grating structure is formed; and

a control system operatively coupled to the measurement system and one or more fabrication components to selectively control one or more of the fabrication components or operating parameters of the fabrication components to mitigate overlay error and to bring critical dimensions within acceptable tolerances based upon one or more of the concurrent measurements taken by the measurement system.

2. The system of claim 1 wherein the structure, to facilitate concurrent measurement of one or more critical dimensions and overlay via scatterometry, comprises one or more underlying gratings that facilitate overlay measurements and one or more overlying gratings that facilitate critical dimension measurements.

3. The system of claim 2 wherein the overlying gratings comprise elongated raised portions.

4. The system of claim 2 wherein a first grouping of the overlying gratings comprises multiple elongated portions oriented substantially in parallel with one another to facilitate measuring overlay in a first direction.

5. The system of claim 2 wherein a second grouping of the overlying gratings comprises multiple elongated portions substantially in parallel with one another and oriented substantially perpendicular to the first grouping to facilitate measuring overlay in a second direction.

6. The system of claim 1 wherein the structure, to facilitate concurrent measurement of one or more critical dimensions and overlay via SEM, comprises one or more gratings formed in a material layer of the structure and one or more features formed within a resist layer of the structure, the material layer comprising at least one of polysilicon, nitride, and silicon dioxide.

7. The system of claim 6 wherein the SEM can interrogate the features for critical dimensions and portions of the gratings extending from the features for a determination of at least one of overlay and overlay error.

8. The system of claim 6 wherein the structure is formed within an implant layer of a flash memory product.

9. The system of claim 6 wherein the measurement system comprises:

a beam generating system from which an electron beam is generated and projected through an electromagnetic lens onto the structure; and

one or more detectors that detect electrons reflected off of the structure.

10. The system of claim 1 wherein the measurement system includes one or more light sources that direct light incident to the gratings;

and

one or more light detecting components that collect light emitted from the gratings, the emitted light varying in at least one of angle, intensity, phase and polarization as the fabrication process progresses.

11. The system of claim 10 wherein the emitted light can be analyzed to generate one or more signatures for comparison to one or more stored signatures to determine whether one or more critical dimensions fall outside of acceptable tolerances and/or whether overlay error is occurring.

12. The system of claim 10 wherein the emitted light can be analyzed by an algorithm to obtain a measurement in order to determine whether one or more critical dimensions fall outside of acceptable tolerances and/or whether overlay error is occurring.

13. The system of claim 1 wherein the control system controls at least one of alignment, exposure, post exposure baking, development, photolithography, etching, polishing, deposition, exposure time, exposure intensity, exposure magnification, exposure de-magnification, movement via a stepper motor, temperatures associated with the process, pressures associated with the process, concentration of gases applied to the process, concentration of chemicals applied to the process, flow rates of gases applied to the process, flow rates of chemicals applied to the process, excitation voltages associated with the process, illumination time, illumination intensity, concentration of slurry applied during CMP, rate of flow of slurry applied during CMP, degree of abrasiveness of slurry applied during CMP, pressure applied during CMP, baking time, balking temperatures and etchant concentrations.

14. A system that facilitates concurrent measurement of one or more critical dimensions and overlay during a semiconductor fabrication process via scatterometry comprising;

one or more underlying gratings formed within an underlying layer of at least a portion of a wafer undergoing the semiconductor fabrication process that facilitates measurement of overlay by analyzing light reflected from the gratings;

one or more overlying gratings formed over the underlying gratings on an overlying layer of at least a portion of the wafer that facilitates measurement of one or more critical dimensions by analyzing reflected electrons; and

one or more logical grids mapped to the wafer comprising one or more locations in which the underlying and overlying gratings for use in concurrent measurements is formed.

15. The system of claim 14 wherein the overlying gratings comprise elongated raised portions.

16. The system of claim 14 wherein a first grouping of overlying gratings comprises multiple elongated portions oriented substantially in parallel with one another to facilitate measuring overlay in a first direction.

17. The system of claim 14 wherein a second grouping of overlying gratings comprises multiple elongated portions substantially in parallel with one another and oriented substantially perpendicular to the first grouping to facilitate measuring overlay in a second direction.

18. A system that facilitates concurrent measurement of one or more critical dimensions and overlay error during a semiconductor fabrication process via a scanning electron microscope (SEM) comprising:

one or more features formed in a resist layer of at least a portion of a wafer undergoing the fabrication process that facilitates measurement of one or more critical dimensions by analyzing electrons from an electron beam directed at and reflected from at least the portion of the wafer; and

one or more gratings formed under the features in a polysilicon layer of at least a portion of the wafer by mapping the wafer into one or more blocks comprising one or more locations in which the one or more gratings for use in the concurrent measurement is formed, portions of the gratings extending out from tinder the features facilitating a determination of overlay error by analyzing reflected electrons, the features are formed within an implant layer of a flash memory product.

19. A method for monitoring and controlling a semiconductor fabrication process comprising:

providing a plurality of wafers undergoing the fabrication process;

mapping the plurality of wafers into one or more logical grids comprising one or more portions in which a grating structure for use in concurrent measurements is formed;

concurrently measuring one or more critical dimensions and overlay in a wafer undergoing the fabrication process;

determining if one or more of the critical dimensions are outside of acceptable tolerances;

determining whether an overlay error is occurring;

developing control data based upon one or more concurrent measurements when at least one of an overlay error is occurring and one or more of the critical dimensions fall outside of acceptable tolerances; and

feeding forward or backward the control data to adjust one or more fabrication components or one or more operating parameters associated with the fabrication components when at least one of an overlay error is occurring and one or more of the critical dimensions fall outside of acceptable tolerances to mitigate overlay error and/or to bring critical dimension within acceptable tolerances.

20. The method of claim 19 further comprising:

forming at least one grating structure on at least a portion of the wafer that facilitates concurrent measurements of one or more critical dimensions and overlay using at least one of scatterometry and scanning electron microscope (SEM) techniques.

21. The method of claim 19 wherein scatterometry is utilized to concurrently measure one or more critical dimensions and overlay, the method further comprising:

forming one or more underlying gratings within an underlying layer of at least a portion of the wafer that facilitates measurement of overlay by reflecting light directed incident to the gratings; and

forming one or more overlying gratings over the underlying gratings on an overlying layer of at least a portion of the wafer that facilitates measurement of one or more critical dimensions by reflecting the incident light.

22. The method of claim 19 wherein SEM is utilized to concurrently measure one or more critical dimensions and overlay, the method further comprising:

forming one or more features in a resist layer of at least a portion of the wafer that facilitates measurement of one or more critical dimensions by analyzing electrons emitted from an electron beam directed at and reflected from at least the portion of the wafer; and

forming one or more gratings under the features in a polysilicon layer of at least a portion of the wafer, portions of the gratings extending out from under the features facilitating a determination of overlay error by analyzing the reflected electrons.

23. A system that monitors and controls a semiconductor fabrication process comprising:

means for mapping one or more logical grid blocks to at least one wafer;

means for forming at least one grain structure according to the one or more logical grid blocks associated with at least a portion of the wafer undergoing the fabrication process that facilitates concurrent measurements of one or more critical dimensions and overlay;

means for directing at least one of light and electrons onto the structure;

means for collecting light reflected from the structure;

means for analyzing the reflected light to determine whether at least one of an overlay error is occurring and one or more critical dimensions full outside of acceptable tolerances; and

means for adjusting one or more fabrication components or one or more operating parameters associated with the fabrication components when at least one of overlay error is occurring and one or more of the critical dimensions fall outside of acceptable tolerances to mitigate overlay error and/or to bring critical dimension within acceptable tolerances.

24. The system of claim 23 wherein the concurrent measurements are performed using at least one of scatterometry and SEM.

25. The system of claim 23 further comprising means for developing control data based upon one or more of the concurrent measurements when at least one of an overlay error is occurring and one or more of the critical dimensions fall outside of acceptable tolerances.