Flash memory device and architecture with multi level cells
First Claim
1. A multilevel FLASH cell architecture comprising:
- at least one FLASH cell;
a plurality of reference generators;
a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators;
the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and
providing outputs; and
translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the plurality of reference generators are coupled together such that a first reference generator provides a base current and subsequent reference generators add sequentially increasing amount of delta current to the base current.
2 Assignments
0 Petitions
Accused Products
Abstract
A FLASH memory has an array of FLASH cells that each store N multiple bits of information as charge stored on a floating gate. Reference voltages or currents are generated for each boundary between the 2N states or levels and for an upper limit and a lower limit reference for each state. A selected bit line driven by a selected FLASH cell generates a sense node that is compared to a full range of 3*2N−1 comparators in parallel. The compare results are decoded to determine which state is read from the selected FLASH cell. An in-range signal is activated when the sense node is between the upper and lower limit references. The target programming count or programming pulses is adjusted during calibration to sense in the middle of the upper and lower limit references. Margin between references is adjusted by calibration codes that select currents for summing.
93 Citations
27 Claims
-
1. A multilevel FLASH cell architecture comprising:
-
at least one FLASH cell; a plurality of reference generators; a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators;
the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and
providing outputs; andtranslation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the plurality of reference generators are coupled together such that a first reference generator provides a base current and subsequent reference generators add sequentially increasing amount of delta current to the base current. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A multilevel FLASH cell architecture comprising:
-
at least one FLASH cell; a plurality of reference generators; a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators;
the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and
providing outputs; andtranslation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the translation logic detects underprogramming and overprogramming of a FLASH cell by comparing the sensing node to limits for each state.
-
-
23. A multilevel FLASH cell architecture comprising:
-
at least one FLASH cell; a plurality of reference generators; a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators;
the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and
providing outputs; andtranslation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the most significant bit (MSB) and the least significant bit (LSB) of the state is provided from the translation logic, and wherein the translation logic detects if the current state of the FLASH cell matches the desired data to indicate successful data validation. - View Dependent Claims (24, 25)
-
-
26. A multilevel FLASH cell architecture comprising:
-
at least one FLASH cell; a plurality of reference generators; a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators;
the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and
providing outputs;translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell; and a control engine for decoding received addresses wherein the row address causes a row of cells to be activated and a column address activates the reference generators and a multichannel cell address.
-
-
27. A multilevel FLASH cell architecture comprising:
-
a memory cell array wherein a plurality of reference generators; a plurality of comparators coupled to the memory cell array via a sensing node and coupled to the plurality of reference generators;
the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and
providing outputs;translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the memory cell array; and a I/O buffer coupled to the translation logic.
-
Specification