Charge mode active pixel sensor read-out circuit

• US 7,088,394 B2
• Filed: 07/09/2001
• Issued: 08/08/2006
• Est. Priority Date: 07/09/2001
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rossi, Giuseppe, Barna, Sandor L.
• Primary Examiner(s): Ometz, David
• Assistant Examiner(s): TRAN, NHAN T
• Application Number:
  US09/901,280
• Publication Number:
  US 20030007083A1
• Time in Patent Office: 1,856 Days
• Field of Search: 348294-324, 250/208.1, 378/98.8
• US Class Current: 348/294
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors

Abstract

An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from respective subgroups of sensors, and group select circuits are coupled to outputs from subgroup select circuits associated with respective ones of the groups. A bus is coupled to receive outputs from the group select circuits. A controller can provide control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals from the sensors to the bus one sensor at a time.

Claims

1. An apparatus comprising:

groups of image sensors, each group comprising subgroups of sensors;

subgroup select circuits, each of which is coupled to an output from a respective subgroup of sensors;

group select circuits, each of which is coupled to outputs from subgroup select circuits associated with a respective one of the groups;

a first bus for each group coupled to the outputs of the associated subgroup select circuits;

a common output bus for receiving signals from each of the groups, the common output bus connected to the readout circuit;

a controller for providing control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals in a charge mode manner from the sensors to a readout circuit one sensor at a time; and

a first isolation circuit coupled to each first bus for selectively isolating each group from the readout circuit, the first isolation circuit comprising a switch for selectively connecting the first bus to a predetermined voltage.

2. The apparatus of claim 1 wherein the sensors comprise active pixel sensors.

3. The apparatus of claim 1 further comprising a second bus coupled to the outputs of the group select circuits and the readout circuit.

4. The apparatus of claim 1 wherein the number of group select circuits is approximately equal to the square root of the number of subgroup select circuits.

5. The apparatus of claim 1 wherein a ratio of the number of subgroup select circuits to group select circuits is in a range of 10:

1 and 40;

1.

6. The apparatus of claim 5 wherein the ratio is in a range of 15:

1 and 30;

1.

7. The apparatus of claim 1 wherein each group select circuit comprises a transistor switch with a respective gate terminal for receiving a control signal from the controller, wherein when the switch is turned on, the group select circuit is enabled to pass signals from associated subgroup select circuits to the first bus, and when the switch is turned off, the group select circuit is disabled from passing signals from the associated subgroup select circuits to the first bus.

8. The apparatus of claim 7 wherein each subgroup select circuit comprises a transistor switch with a respective gate terminal for receiving a control signal from the controller, wherein when the subgroup select circuit switch is turned on, the subgroup select circuit is enabled to pass signals from an associated subgroup of sensors, and when the subgroup select circuit switch is turned off, the subgroup select circuit is disabled from passing signals from the associated subgroup of sensors to the first bus.

9. The apparatus of claim 8 wherein the controller is configured for generating the control signals to enable and disable the group select circuit switches and the subgroup select circuit switches in a predetermined sequence.

10. The apparatus of claim 9 wherein the controller is configured to provide the control signals to enable the switches in the group select circuits sequentially, and, while a particular group select switch is enabled, to enable the subgroup select circuits associated with the particular group select circuit sequentially, one at a time.

11. The apparatus of claim 1 wherein the controller is configured to enable and subsequently disable each group select circuit, one at a time, in a sequential manner.

12. The apparatus of claim 1 wherein each group select circuit comprises a pair of NMOS transistor switches.

13. The apparatus of claim 3 comprising:

supergroups of sensors;

supergroup select circuits, each of which is coupled to outputs from group select circuits associated with a respective one of the supergroups; and

a second isolation circuit coupled to each second bus for selectively isolating each supergroup from the readout circuit, the second isolation circuit comprising a switch for selectively connecting the second bus to a predetermined voltage,

wherein the controller is configured to provide control signals to the supergroup select circuits to selectively enable a supergroup select circuit to pass a signal from the second bus to a third, common output bus.

14. The apparatus of claim 13 wherein an output of each supergroup select circuit is coupled electrically to a common output bus.

15. The apparatus of claim 13 wherein each supergroup select circuit comprises a transistor switch with a respective gate terminal for receiving a control signal from the controller.

16. The apparatus of claim 1, wherein the predetermined voltage is one of a supply voltage for the apparatus or a ground potential.

17. The apparatus of claim 1, wherein the common output bus is connected between outputs from the group select circuits and the readout circuit.

18. The apparatus of claim 13, wherein the common output bus is connected between outputs from the supergroup select circuits and the readout circuit.

19. A method of obtaining a readout of a pixel sensor array comprising:

organizing pixel sensors of an array into groups comprising a plurality of subgroups of sensors, the outputs of each subgroup coupled to an associated subgroup select circuit and the outputs of each subgroup select circuit coupled to an associated group select circuit;

selectively enabling a group select circuit and a subgroup select circuit to allow a signal from each sensor in said subgroup to pass sequentially and in a charge mode manner to a readout circuit electrically connected to said group select circuit;

sensing a charge at the readout circuit; and

selectively isolating from said readout circuit the groups of pixels not associated with the selectively enabled group select circuit by disabling the subgroup select circuits and group select circuits not associated with the selectively enabled group select circuit and applying a predetermined voltage to at least one first bus coupled to the disabled group select circuits by operating a switch coupled to the at least one first bus.

20. The method of claim 19 further comprising the step of organizing groups of subgroups of said sensors into supergroups, wherein the outputs of group select circuits associated with a supergroup are connected to a respective supergroup select circuit.

21. The method of claim 20 further comprising the step of coupling each supergroup select circuit to an associated second bus, wherein the readout signals from each sensor in said supergroup will travel through said second bus.

22. The method of claim 21 further comprising the step of selectively applying the predetermined voltage at each second bus.

23. The method of claim 19, wherein the predetermined voltage is one of a supply voltage for the array or a ground potential.