Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code

• US 7,089,483 B2
• Filed: 03/04/2004
• Issued: 08/08/2006
• Est. Priority Date: 07/12/1999
• Status: Expired due to Fees

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Inventors: Fitzpatrick, Kelly, McEwen, Peter
• Primary Examiner(s): TORRES, JOSEPH D
• Application Number:
  US10/793,414
• Publication Number:
  US 20040181732A1
• Time in Patent Office: 887 Days
• Field of Search: 714/795, 714/792, 375/341, 375/265
• US Class Current: 714/795
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 2020/1863 wherein the Viterbi algorithm is used for decoding the error correcting code
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.

Claims

1. A maximum likelihood detector for use within a partial response channel having a channel transfer function and passing user information sequences encoded into code words in accordance with a channel code, the maximum likelihood detector comprising:

a channel sampler for generating raw samples from the code words;

a channel equalizer for generating equalized samples from the raw samples using the channel transfer function;

a first-stage detector for generating unchecked code words from the equalized samples, wherein the first-stage detector is matched to the channel transfer function and the first-stage detector is not matched to the channel code; and

a second-stage post-processor for generating corrected code words from the raw samples and the unchecked code words, wherein the second-stage post-processor is matched to the channel code and includes;

a parity checker for generating parity error signals from parity errors in the unchecked code words, wherein the parity errors are due to error-events in the unchecked code words;

an error metrics generator for generating decision metrics from the raw samples and the unchecked code words using the channel transfer function;

a decision metrics filter for generating most likely error-events by comparing the error-events with predetermined error-events using the channel code; and

a code word corrector that generates the corrected code words by removing the most likely error-events from the unchecked code words using the parity error signals and the decision metrics, wherein the most likely error-events include one error-event contained within a single unchecked code word, one error-event straddling two adjacent unchecked code words, multiple error-events contained within a single unchecked code word, and multiple error-events at least one of which straddles two adjacent unchecked code words.

2. The maximum likelihood detector set forth in claim 1 wherein the channel sampler is an analog-to-digital converter, the channel equalizer is a digital finite impulse response filter, and the first-stage detector is a Viterbi detector.

3. The maximum likelihood detector set forth in claim 1 wherein the user information sequences are encoded using a channel modulation code.

4. The maximum likelihood detector set forth in claim 1 wherein the user information sequences include user information blocks and appended error correction syndromes.

5. The maximum likelihood detector set forth in claim 1 embodied within a magnetic recording and playback device.

6. The maximum likelihood detector set forth in claim 5 wherein the magnetic recording and playback device is a disk drive.

7. The maximum likelihood detector set forth in claim 5 wherein the magnetic recording and playback device is a tape drive.

8. The maximum likelihood detector set forth in claim 1 wherein the channel transfer function is a new partial response target having a discrete-time transfer function of 14+8D−

8D²−

10D³−

4D⁴ where D is a unit time delay operator.

9. The maximum likelihood detector set forth in claim 1 wherein the channel code includes one of a single bit parity code, a two bit interleaved parity code, and a three-bit modulo-7 parity code having a weighting vector {1 2 4} repeated.