2V SPDT switch for high power RF wireless applications

• US 7,092,677 B1
• Filed: 09/05/2002
• Issued: 08/15/2006
• Est. Priority Date: 09/05/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Zhang, Shuyun, McMorrow, Robert J.
• Primary Examiner(s): LE, LANA N
• Application Number:
  US10/235,361
• Time in Patent Office: 1,440 Days
• Field of Search: 455/78, 455/77, 455/79, 455/80, 455/81, 455/82, 455/83
• US Class Current: 455/78
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A SPDT switch includes an antenna port. A transmitter section is coupled to a transmitter port. The transmitter section includes a plurality of transistors that are coupled in series relative to each other. A receiver section is coupled to a receiver port. The receiver section includes a plurality of transistors that are coupled in series relative to each other, so that when the transmitter section transmits high power to the antenna port, the receive section is effectively off to provide isolation to the receive port. The receiver port is coupled to the receiver section using at least one external capacitor. The at least one external capacitor is used to improve the power handling capability and harmonic performance of the switch.

Claims

1. A SPDT switch comprising:

an antenna port;

a transmitter section that is coupled to a transmitter port, said transmitter section including a plurality of first transistors that are coupled in series relative to each other wherein the drain of each successive first transistor is connected to the source of an adjacent transistor; and

a receiver section that is coupled to a receiver port, said receiver section including a plurality of second transistors that are coupled in series relative to each other wherein the drain of each successive second transistor is connected to the source of an adjacent transistor, so that when said transmitter section transmits high power to said antenna port, the receiver section is effectively off to provide isolation to said receive port;

wherein

said receiver port is coupled to said receiver section using at least one first external capacitor, said at least one first external capacitor being used to improve the power handling capability and harmonic performance of the switch;

said transmitter port is coupled to said transmitter section using at least one second external capacitor, said second external capacitor being used to improve the power handling capability and harmonic performance of the switch.

2. The SPDT switch of claim 1, wherein said plurality of transistors of said transmitter section are each coupled to a set of resistors.

3. The SPDT switch of claim 2, wherein said resistors are coupled to a DC voltage control source.

4. The SPDT switch of claim 1, wherein said plurality of transistors of said receiver section are each coupled to a set of resistors.

5. The SPDT switch of claim 4, wherein said resistors are coupled to a DC voltage control source.

6. The SPDT switch of claim 1, wherein said antenna port is coupled to said transmitter section.

7. The SPDT switch of claim 1, wherein said antenna port is coupled to said receiver section.

8. The SPDT switch of claim 1, wherein said antenna port is coupled to said transmitter section using at least one third external capacitor, said at least one third external capacitor being used to improve the power handling capability and harmonic performance of the switch.

9. The SPDT switch of claim 1, wherein said antenna port is coupled to said receiver section using at least one fourth external capacitor, said at least one fourth external capacitor being used to improve the power handling capability and harmonic performance of the switch.

10. The SPDT switch of claim 1, wherein said gates of said transistors of said transmitter section are connected to resistors.

11. The SPDT switch of claim 1, wherein said gates of said transistors of said receiver section are connected to resistors.

12. A method of minimizing distortion in a SPDT switch, said method comprising:

providing an antenna port;

providing a transmitter section that is coupled to a transmitter port, said transmitter section including a plurality of first transistors having a plurality of gates are coupled in series relative to each other wherein the drain of each successive first transistor is connected to the source of an adjacent transistor;

providing a receiver section that is coupled to a receiver port, said receiver section including a plurality of second transistors having a plurality of gates are coupled in series relative to each other wherein the drain of each successive second transistor is connected to the source of an adjacent transistor, so that when said transmitter section transmits high power to said antenna port, the receive section is effectively off to provide isolation to said receive port and minimizing distortions;

using at least one first external capacitor to be coupled to said receiver port, said at least one first external capacitor is used to improve the power handling capability and harmonic performance of the switch; and

using at least one second external capacitor to be coupled to said transmitter port, said at least one external capacitor is used to improve the power handling capability and harmonic performance of the switch.

13. The method of claim 12, wherein said plurality of transistors of said transmitter section are each coupled to a set of resistors.

14. The method of claim 13, wherein said resistors are coupled to a DC voltage control source.

15. The method of claim 12, wherein said plurality of transistors of said receiver section are each coupled to a set of resistors.

16. The method of claim 15, wherein said resistors are coupled to a DC voltage control source.

17. The method of claim 12, wherein said antenna port is coupled to said transmitter section.

18. The method of claim 12, wherein said antenna port is coupled to said receiver section.

19. The method of claim 12, wherein said antenna port is coupled to said transmitter section using at least one third external capacitor, said at least one third external capacitor used to improve the power handling capability and harmonic performance of the switch.

20. The method of claim 12, wherein said antenna port is coupled to said receiver section using at least one fourth external capacitor, said at least one fourth external capacitor used to improve the power handling capability and harmonic performance of the switch.

21. The method of claim 12, wherein said gates of said transistors of said transmitter section are connected to resistors.

22. The method of claim 12, wherein said gates of said transistors of said receiver section are connected to resistors.