Multistandard video decoder and decompression system for processing encoded bit streams including start codes and methods relating thereto

• US 7,095,783 B1
• Filed: 10/12/2000
• Issued: 08/22/2006
• Est. Priority Date: 06/30/1992
• Status: Expired due to Fees

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Robbins, William P, Wise, Adrian P, Boyd, Kevin J, Jones, Anthony M, Sotheran, Martin W, Claydon, Anthony Peter J, Finch, Helen R
• Primary Examiner(s): VO, TUNG T
• Application Number:
  US09/689,120
• Time in Patent Office: 2,140 Days
• Field of Search: 375/240.1, 375/240.16, 375/24.17, 375/240.15, 375/240.01, 382/246, 712/300
• US Class Current: 375/240.01
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.

Claims

1. A pipelined video decoder and decompression system for handling a plurality of separately encoded bit streams, said system comprising:

a start code detector responsive to a single serial bit stream for generating control tokens and data tokens, said token including a plurality of data words, each data word having an extension bit which indicates a presence of additional words therein so that said start code detector detects overlapping start codes in said bit stream, a first start code thereby being ignored and a second start code used to create start code tokens;

a token decode circuit interactively associated with said start code detector, said token decode circuit for recognizing certain of said tokens as control tokens pertinent to a respective processing stage and for passing unrecognized control tokens to a succeeding stage; and

a reconfigurable decode and parser processing means responsive to a recognized control token for reconfiguring a particular stage to handle an identified data.

2. The system as recited in claim 1 further comprising first and second registers, said first register positioned as an input of said decode and parser means and said second register positioned as an output of said decode and parser means.

3. The system according to claim 1 wherein said single serial bit stream of digital bits includes separately encoded pairs of control codes and corresponding data carried therein.

4. The system according to claim 1 wherein said tokens are altered by said processing stages.